Professor Lee, Yong Surk. References. Topics Microprocessor & microcontroller. High Performance Microprocessor Architecture Overview
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1 This lecture was mae by a generous contribution of C & S Technology corporation. ( There is no copyright on this lecture. Processor Laboratory homepage, ( inclues many microprocessor relate on-line lectures that can be own loae free of charge. Professor Lee, Yong Surk 1973 : B.S., Electrical Eng., Yonsei niv : Ph.D, niv. of ichigan, Ann Arbor 1982 ~ 1992 : Designe microprocessors in silicon valley, California Designe Pentium at Intel (1989 ~ 1992) 1993 ~ : Professor at Yonsei niversity 1 2 High Performance icroprocessor Architecture Overview January Electrical & Electronic Engineering Department, Yonsei niversity, Seoul, Korea Professor Lee, Yong Surk Homepage: yonglee@yonsei.ac.kr Tel : References [1] J.L.Hennessy & D.A.Patterson, Computer Architecture, a Quantitative Approach, Secon (Thir) Eition, organ Kaufmann Publishers, 1996 (2003) [2] N.Alexanriis, Design of icroprocessor Base Systems, Prentice Hall, [3] D. Sima,, T. Fountain, P. Kacsuk, Avance Computer Architectures, a Design Space Approach, Aison - esley, 1997 [4] IEEE Stanar Committee, IEEE Stanar for Binary Floating-Point Arithmetic, ANSI / IEEE St [5] icroprocessor Report,.PRONLINE.CO 5 Topics icroprocessor & microcontroller & C Superscalar & VLI Pipelining Branch strategy Cache memory / Floating point unit Clocking Top-own esign 6
2 True n-bit n icroprocessor n-bit register file n-bit ata path ( +, -,, x, / ) n-bit bus ( in & out ) µ P Classification Performance Low eium 4, 8 bits 16, 32 bits transistors Below a few tens of 1000s Zilog Z-80, Intel 8051 AR, Hitachi SH High 32, 64 bits Above a few million Pentium, ltrasparc, Alpha 7 µp P vs. µc C (1) Data with Clock freq icro - processor 32, 64 bits 4, 8, 16, 32 bits Above a few hunre Hz icro- controller Below a few hunre Hz µp P vs. µc C (2) ultiplier Divier icro - processor Booth multiplier SRT ivier icro - controller ses AL ses AL Architecture Cache,, floating point unit, pipelining Design methoology se Top - own Not use Top own Bottom -up 8 Transistor Application Cost Above a few million Computer CP High Below a few million Controller Low 9 (Complex Set Computer) (Reuce Set Computer) 10 vs. (1) (Ref.[1, 2]) instruction length execution time Pipelining (Pentium) A few hunres Variable ( bytes) Variable (1-300 clk/ inst) Not efficient A few tens Fixe (44 bytes) Fixe (1 clk/ inst) Efficient 11
3 vs. (2) Control registers Data memory access Design effort (Pentium) icrocoe Small ( about 8) ory operans 5-10 X 600(man man- year) Harwire Large ( ) Loa, store only 1 X 60(man man- year) 12 = Temp 1 Temp 2 R 1 + R 1 +Temp 1 Temp 2 R 2 R 3 R 1 + R 2 R3 microinstruction = instruction 13 Intel Pentium4 () Easy to sort from memory Prefix 0 4 Op coe o R / SIB (bytes) Ar isp Imm ata ~17 byte length 14 Easy to ecoe Suitable for superscalar Suitable for pipelining Alpha () icroprocessor Spee (per task) AL 31 0 Opcoe Ra Rb SBZ 0 Function Rc = (NI( ) X (CPI( ) X C Branch Opcoe Ra or_isp NI : execute s Loa, Store Floating point Opcoe Opcoe Ra Fa Rb Fb or_isp Function Fc 15 CPI : Clocks Per C : Clock perio (=1/ clock frequency ) 16
4 NI ( execute Inst ) CPI ( Clock Per Inst) C (1/ frequency) Spee 1X 1X - 300X 1X - 2X Slow 2X 1X 1X Fast 17 Benchmark IPS (illion Inst Per Secon) VAX IPS - VAX 11/780 Dhrystone, hetstone, Linpack - benchmark engineering SPEC int - 89, 92, 95, 00, 04 SPEC SPEC fp - 89, 92, 95, 00, 04 (.SPEC.ORG) 18 Alpha 21264C IPS R14000 Sun ltra- Sparc-3 Intel Pentium-4 Five Stage Pipeline (Ref.[1, 2]) Clock freq. transistor Issue rate SPEC00b (int/ fp) Power consumption 1000Hz 500Hz 1000Hz 15.4m 7.2m 29m 2000Hz 42m / / / / icroprocessor Report, December, 2001 (.PRONLINE.CO) F : Inst fetch (inst access) & inc D : Inst ecoe & regrea E : AL op or ar calculation : Data access : Reg writeback 20 Alpha Pipeline F D Arr Iss E1 E2 Clock Scalar µp F : Fetch D : Decoe Arr : Arrange to issue Issue : Issue & reg rea E 1 : AL operation E 2 : Data access : rite back 21 I #1 I #2 I #3 I #4 I #5 1 inst per clock (I) 22
5 Clock Superscalar µp I #1 I #2 I #3 I #4 I #5 I #6 2 inst per clock (I) 23 Superscalar Data epenency R 1 R 2 + R 3 R 5 R 1 + R 4 Compiler minimizes ata epenency Dynamic scheuling by harware ost superscalar µps can issue 3 6 instructions maximum per cycle Compatibility 24 VLI (Very Long or) µp Loa Store A Compare FP a FP mult Branch #1 #2 Int AL Int AL FP AL FP mult ultiporte register file Branch unit 25 VLI (Ref. [3], p176) Static scheuling by compiler Complex compiler, simple harware No compatibility Cannot program in assembly language 26 Scalar µp Havar Architecture Clock I #1 I #2 I #3 I #4 I #5 F D E ory access 27 CP Inst bus Data bus Inst memory Data memory 28
6 Von Neumann Architecture Sub R 3, R 1, R 2 ; R 3 R 1 - R 2 CP Inst bus Data bus nifie memory F : Inst fetch & inc D : Inst ecoe & R 1, R 2 rea E : Temp R 1 - R 2, status available Two - port memory : No op : : R 3 temp ; write status reg Loa R 3, R 1, R 2 ; R 3 [R 1 + R 2 ] Store R 1, R 2, R 3 ; [R 1 + R 2 ] R 3 F : Inst fetch & inc F : Inst fetch & inc D : Inst ecoe & R 1, R 2 rea D : Inst ecoe & R 1, R 2, R 3 rea E : R 1 + R 2 ; ar calculation E : R 1 + R 2 ; ar calculation : [R 1 + R 2 ] ; ata rea : [R 1 + R 2 ] R3 : R 3 [R 1 + R 2 ] 31 : No op ; ata write 32 Br 85 ; Branch to + 85 F : Inst fetch & inc + 4 X FF FF FF FF A BR ADDR D : Inst ecoe & + 85 calculation E : + 85 ; branch : No op Inst D e c o e R E G X A L Data X : No op 33 34
7 Ege Triggere S Flip-Flop Flop Inst Cache iss Cache miss penalty D Q D FF Q I #1 I #2 I #3 I #4 I #5 Inst miss Loa Interlock Frozen R 1 [R 2 +85] Bypass In 0 X 1 D Q Flip flop Out Avance R 4 R 1 + R 3 XXX Freeze 37 0 : Freeze 1 : Avance 38 In D Q Flip flop Out Data Bypassing (Forwaring) Clock AND Freeze Clock Freeze 1 cycle frozen R 1 R 2 +R 3 R 5 R 1 -R 4 Bypass 39 40
8 + 4 FF FF FF FF X Inst D e c o e A R E G BR ADDR X A L Bypass Data X 41 Branch Strategy (Ref.[1]) BTB (Branch Target Buffer) Delaye branch Preict - not - taken 42 Delaye Branch Branch Delay slot Target fetch F D E F D E Target aress F D E Compiler has to fill the elay slot 43 Preict - not - taken ntaken branch i + 1 i + 2 Taken branch F i + 1 Target aress Branch target fetch Flushe! XXX XXX XXX XXX 44 µp P System Fast CP Reg file SRA Cache mem DRA ain mem Slow H.D. 8 reg 512KB 256B 30GB icroprocessor Clock Frequency (Perio) 10Hz(100nS) 100Hz(10nS) DRA Access Time 100nS 50nS Block size (16 64B) Page size (2K 8KB) Hz(1nS) 25nS 46
9 Aress Translation 2 32 = 4G 4KB 4KB 0 Virtual (logical) aress ory anagement nit KB 4KB Physical aress 47 IEEE Floating Point Stanar (Ref. [4]) Single precision Double precision bits S E F bits S E F υ = (-1)( S. e 2 (1.F), e = E - bias 48 0 Integer < < Single precision Double precision < Clocking 1 GHz clock (= 1nS perio) 30cm 2cm 2cm µp P chip FF 1 FF 2 1nS t 3cm metal ( t>0.1ns) 50 Top-Down Design Steps 1. Simulator (C) 20% 2. HDL moel 20% 3. Verification 20% 4. Synthesis, full custom 20% 5. Verification 20% Total 100% 6. Fault graing aitional 20% 51
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