Special Nodes for Interface

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Paul Benson
5 years ago
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5 Special Nodes for Interface SW on processors Chip-level HW Board-level HW

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7 C code VHDL VHDL code retargetable compilation high-level synthesis SW costs HW costs partitioning (solve ILP) cluster SW nodes retargetable compilation SW costs

10 Flow Graphs Program Threads Program Routines

11 formal languages (Esterel) translators CFSMs partitioning partitioned CFSMs translator verification intermediate format simulation formal verification SW synthesis HW synthesis interface synthesis scheduler template + timing constraints S-graph OS synthesis C code BLIF logic synthesis optimized hardware HW interface integration

12 * = + = = while T s T c T b + = = = = = < = + + nw nw nr T(n r )

13 T1 * = = + + = T7 = = + = while T6 = + T2 T4 = = nw nw nr T5 < T(n r ) : T 5 S T (n r ) : T 1, T 6 T3

14 S T (n r ) T2 T6 T1 T5 T3 T7 T(n r ) T1 T3 T2 T(n r ) T5 T6 T7 T1 T3 T5 T2 T(n r ) T6 T7 T1 T3 T2 T5 T(n r ) T6 T7 static scheduling dynamic scheduling static scheduling

15 T1 conditional of while loop T2 body of while loop T5 T3 T4 T(nr) T 1, T 2 : T s T 3 : T c T 4, T 5, T(nr) : T b S T (n r ) : T 2, T 5 H/W delay T1 T3 T4 T2 T5 T(nr) T1 T2 T3 T5 T4 T(nr) context switching polling overhead

16 do do {{ Ti; Ti; _read_hw(&done); while while (1) (1){ { } _read_hw(&done); } while while (!done (!done&& && there there are are some sometis); Tnr; if if (!done) (!done) continue; Tnr; continue; _read_hw(&data1); _read_hw(&data2); scheduler code _read_hw(&datan); _read_hw(&data1); } } _read_hw(&data2); _read_hw(&datan); polling sequences of straight-line code thread code(part of Tnr)

17 Relative Execution Time Number of Polling Operation Relative Overhead Number of Polling Operation

18 File 1 File2 size in bytes All S/W solution Execution time (sec) Co-design with mutual exclusion Co-design by our algorithm

20 ping (input chan(int) a, output chan(int) b) { int x; for (;;) { x=<-a; /* receive */ c2 if (x<0) b x=10-x; c else x=10+x; d b<-=x; /* send */ c1 }} pong (input chan (int) c, output chan(int) d) { int y, z=0; for (;;) { d<-=10; /* send */ c2 y=<-c; /* receive */ c1 z=(z+y) % 345; f }} p1 p2 c2 c2 b c1 c d f c1 system ( ) { chan (int) c1, c2; par { ping (c2, c1); pong (c1, c2); }}

21 p1 p2 p1p2 c2 c2 c2 b c1 b c d f c d c1 c1 f

22 p1 p2 p1 p2 a g a g p3 p3 b d h b d h c e i k c e i k p4 p4 j l j l f f P1 P2 P3

23 p1 p2 p1 p2 a g a g p3 p3 b d h b d h c e i k c e i k p4 p4 j l j l f P1 P2 P3 f P1 P2 P3

24 p1 a p2 g p3 a g b d h b h d h c e i k c i c k e i e k p4 j l j l f P1 P2 P3 f p3p4

26 (period, deadline, computation time)

28 τ τ τ C C C 7 25 =, T = =, T = =, T = worst case Computation time period S = { T } S = { T, T } Scheduling points S = { T, T, T, T } τ τ C C 2C T C > T1 1 + C > T2 sum of computation time demand τ C + C + C > T 1 1 2C 2C + C + C > T C + C > T 1 1 3C + C + C > T 1 3

29 S i = { kt j j =,..., i ; k =,..., } T i T j min {t S i } 1 t i j = C j t T j

30 τ τ τ S = { T } S = { T, T } S = { T, T, T, T } τ τ c, c i, j c : time deviation of task τi at the j th scheduling point, = c, = τ c, = c, = c c, =, =

31 τ τ d ijk : time by whichc k must be reduced to makeτ i schedulable d d d = = d = = τ d = d = d = d =. d = d = d =. d =. d = d =. d = d = D =. Reduce the execution time of τ by 4.5 Bounded by maximum reducible computation time(mrc) Iterate the process with new C1 = C1 - mrc1 = = 1.2 D =. Reduce the execution time of τ by 2.8

32 HW

36 N i c i x i

37 /* k >= 0 */ s=k; while (k<10) { if (ok) j++; else { j=0; ok= true; } k++; } r=j; Code CFG d x x x x x x x 1 = = d = d = d = d = d = d = d = d + d = d = d = d + d = d = d + d = d d Constraints 9

38 0x 1 x 3 10x 1 x 5 1x 1 CFG Constraints

40 N hit hit j x i j + i.. i i n j i miss miss ( ci. j xi. j c ) miss hit i. j + x i. j, j = x = x 1,2,..., n i x i u. v = p( u. v, i. j) = u, v u. v p( s, u. v) = 1 p( i. j, u. v) hit i j + p( i. j, i. j) x. p( s, i. j) p( i. j, i. j)

46 C C++ VHDL instruction set spec pattern set structural graph resource classes graph rewrite parallel matching and covering BDS global scheduling register assignment compaction assembly, linking machine code

47 system description (C, DFL) processor description (nml) instruction set, structure statistics (operation patterns, instruction set utilization) flow graph refinement code selection register allocation bit alignment scheduling CDFG library instruction set graph code assembly machine code

48 architecture design ISDL AVIV source code C/C++ ISDL assembler generator compiler front end SUIF compiler assembly binary assembler back end simulation environment

49 ' - basic block: a=b+3 c=2*d e=(c-a)' ' U1 transfernode split-node - U1 - U2 * + 2 d b 3 Basic Block DAG * U2 * U3 + U1 + U2 + U3 databus U1 U2 U3 IM 2 IM d DM b DM 3 IM ADD(+) SUB(-) COMP(') ADD(+) MUL(*) SUB(-) ADD(+) MUL(*) DM Split-Node DAG Target VLIW Architecture

50 Explore possible split-node functional unit assignments - Estimate cost of assignment - Select several lowest cost assignments to explore in further detail Foreach selected assignment - Insert required data transfers - Generate all maximal groupings of nodes that could be executed in parallel - Select a minimal-cost set of maximal groupings that covers all nodes Final solution is the lowest-cost solution found above

51 ' U1 transfernode MUL (U2) 3 2 ADD (U1) 4 ADD (U2) split-node 3 ADD (U3) - U1 - U2 0 SUB (U1) MUL (U3) 2 ADD (U1) 3 3 ADD (U2) 4 ADD (U3) * U2 * U3 + U1 + U2 + U3 0 COMP (U1) 2 IM d DM b DM 3 IM 1 SUB (U2) Split-Node DAG

ECE 5775 (Fall 17) High-Level Digital Design Automation. Control Flow Graph

ECE 5775 (Fall 17) High-Level Digital Design Automation Control Flow Graph Announcements ECE colloquium on Monday 9/11 from 4:30pm, PHL 233 Smart Healthcare by Prof. Niraj Jha of Princeton Lab 1 is due