Embedded Systems 23 BF - ES

Transcription

1 Embedded Systems

2 Measurement vs. Analysis REVIEW Probability Best Case Execution Time Unsafe: Execution Time Measurement Worst Case Execution Time Upper bound Execution Time typically huge variations in ET depending on input, cache effects, cannot be covered within product development time rules of thumb add safety margins: pessimistic? optimistic? - 2 -

3 Path Analysis by Integer Linear Programming (ILP) REVIEW Execution time of a program = Execution_Time(b) x Execution_Count(b) Basic_Block b ILP solver maximizes this function to determine the WCET Program structure described by linear constraints automatically created from CFG structure needs info about loop/recursion bounds additional linear constraints may be added to exclude infeasible paths (contradictory conditions, ) - 3 -

4 Timing Analysis REVIEW 1. For each instruction, determine possible ET in context: Determine possible processor behavior at instruction Exclude timing accidents when context renders them impossible Determine instruction WCET and BCET based on this 2. Accumulate across basic blocks Determines safe bounds for WCET and/or BCET for basic blocks (with contextual info. inherited) 3. Worst-case Path Determination Maps cost-annotated (WCET/BCET) control flow graph to an integer linear program Determines paths with extremal (max./min.) cost Thus determines WCET / BCET of complete task - 4 -

5 Abstract Interpretation REVIEW Semantics-based method for static program analysis Basic idea: Perform the program s computations using abstract values in place of the concrete values Abstract domain = complete semilattice related to concrete domain by abstraction and concretization functions Abstract transfer functions for each statement type = abstract versions of their semantics Join function: combining abstract values from different control-flow paths (lub on lattice) - 5 -

6 Abstract Domain: Must Cache REVIEW Representing sets of concrete caches by their description concrete caches Abstraction z s x t z s x a s z x t x s z t z t x s abstract cache α { } { } {z,x} {s} - 6 -

7 Abstract Domain: Must Cache REVIEW Sets of concrete caches described by an abstract cache concrete caches Concretization abstract cache z, x { { s remaining line filled up with any other block γ { } { } {z,x} {s} - 7 -

8 Lattice for Must Cache REVIEW Set A of elements Information order v Join operator t Top element > Bottom element { } {z} {x} {s} v Better precision: { } { } {z} {s} young old Age more elements in the cache or with younger age. NB. The more precise abstract cache represents less concrete cache states! - 8 -

9 Lattice: Must Cache REVIEW Set A of elements Information order v Join operator t Top element > Bottom element { a } { } { c, f } { d } t { } { } { a, c } { d } young old { c } { e } { a } { d } Age Form the intersection and associate the elements with the maximum of their ages - 9 -

10 Lattice: Must Cache REVIEW Set A of elements Information order v Join operator t Top element > Bottom element { } { } { } { } young old Age No information: All caches possible

11 Lattice: Must Cache REVIEW Set A of elements Information order v Join operator t Top element > Bottom element Dedicated unique bottom element representing the empty set of caches

12 Galois connection Relating Semantic Domains Lattices C, A two monotone functions α and γ Abstraction: α: C A Concretization γ: A C (α,γ) is a Galois connection if and only if γ α w C id C and α γ v A id A Switching safely between concrete and abstract domains, possibly losing precision

13 Abstract Domain Must Cache γ α w C id C concrete caches z s x t z s x a s z x t x s z t z t x s z, x { { s remaining line filled up with any memory block α γ abstract cache { } { } {z,x} {s} safe, but may lose precision

14 Result of the Cache Analysis REVIEW Categorization of memory references Category Abb. Meaning always hit ah The memory reference will always result in a cache hit. always miss am The memory reference will always result in a cache miss. not classified nc The memory reference could neither be classified as ah nor am. WCET: ah improves bound, nc and am count as pot. miss BCET: am tightens bound, nc and ah count as potent. hit

15 Realtime Calculus

16 System Composition Communication Templates Computation Templates SDRAM SDRAM RISC RISC μc μc DSP DSP ECU ECU CAN CAN interface interface Architecture Scheduling and Arbitration Templates SDRA SDRA M RIS RIS C EDF priority EDF WFQ TDMA proportional share FCFS ECU ECU ECU ECU dynamic fixed priority static

17 A Four-Step Approach 1. Abstraction: Build abstract models for first class citizens event streams -> abstract event streams architecture elements -> resource modules application processes -> performance modules 2. Performance Components: Combine performance modules using resource sharing information 3. Performance Network: Combine all models to a network that represents the performance aspects 4. Analysis

18 The Big Picture Application Specification load scenarios Abstract Application application performance process modules abstract event streams T1 T2 T3 event streams mapping abstract loadrelations scenarios performance components Performance Network resource modules Abstract Architecture architecture elements Architecture Specification ARM9 DSP

19 Step 1: Abstract Application Model From a functional model event stream application process (e.g. StateCharts )

20 Step 1: Abstract Functional Units to an abstract application model abstract resource stream abstract event stream performance module

21 Step 2: Build Performance Components Fixed Priority (FP)

22 Step 3 and 4: Compose and Analyze ARM9 Bus DSP1 DSP2 β β β β Application 1 α FP GPS FP Application 2 α β β GPS GPS FP β β β β

23 Event & Resource Models Use arrival curves to capture packet streams: max: 23 1 packets min: 0 1 packets # of packets α u α l Δ Δ time t Δ

24 Arrival curves Arrival curves describe the maximum and minimum number of events arriving in some time interval Δ Examples: periodic event stream periodic event stream with jitter 3 2 u α 3 2 u α 1 l α 1 l α T 2T 3T Δ T 2T 3T Δ T-J T+J

25 Arrival curves Definition: Let R(t) denote the number of events that arrive on an event stream in the time interval [0,t). Then the following holds: l α ( t s) R( t) R( s) u α ( t s), s < t l α (0) u = α (0)

26 Service curves Service curves β u resp. β l describe the maximum and minimum service capacity available in some time interval Δ Example: TDMA bus bandwidth b s bs u β l β T s T-s T T+s 2T

27 Service curves Definition: Let C(t) denote the number of communication or processing cycles available from a resouce of the time interval [0,t). Then the following holds: l β ( t s) C( t) C( s) u β ( t s), s < t l β (0) = β u (0)

28 Workload characterization γ u resp. γ l describe the maximum and minimum service capacity required as a function of the number e of events Example WCET=4 γ u BCET=3 γ l e

29 Workload required for incoming stream Incoming workload u α ( ) ( ) u u Δ = γ α ( Δ) l α ( ) ( ) l l Δ = γ α ( Δ) Upper and lower bounds on the number of events u β ( Δ) = γ 1 ( u β ( Δ) ) l β ( Δ) = γ 1 ( l β ( Δ) )

30 Transformation of Curves by Modules l u [ β, β ] l u [ α, α ] l u [ α ', α ']

31 Performance modules Theorem: Given an event stream described by the arrival curves α u, α l, and a resource described by the service curves β u, β l, then the resulting service is bounded by l β ( Δ) = l sup { β ( λ) 0 λ Δ u α ( λ)}, 0 Δ

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33 Performance Modules v w v w v ( Δ) w( Δ) = min{ v( Δ), w( Δ) } ( Δ) = { v( λ) + w( Δ λ) } v w( Δ) = inf{ v( Δ + λ) w( λ) } 0 inf λ Δ ( Δ) = sup { v( λ) + w( Δ λ) } v w( Δ) = sup{ v( Δ + λ) w( λ) } 0 λ Δ 0 λ 0 λ l u [ β, β ] α u u u = [( α β ) l β u ] β l u [ α, α ] u [ β, β u [ α, α l l ] ] l α β β = [( = l α u β ) l β ( u β α ) 0 ( l β α ) 0 u l = l u ] l β

34 Compose and Analyze I/O bus DSP μp l [ α a, α l [ α a ', α u a u a ] '] fixed prio. prop. share l [ α b, α l [ α b ', α u b u b ] '] fixed prio. fixed prio. l u l u l u β ', β '] [ β ', β '] [ β ', β '] [ β μ ', β '] [ I / O I / O bus bus DSP DSP l P u μp

35 Compose and Analyze l u [ α, α ] l u [ β, β ] delay d service curve β l arrival curve α u b backlog b

36 Application: In-Car Navigation System Car radio with navigation system User interface needs to be responsive Traffic messages (TMC) must be processed in a timely way Several applications may execute concurrently Thiele, ETHZ

37 System Overview MMI Communication NAV RAD DB Thiele, ETHZ

38 Use case 1: Change Audio Volume < 200 ms MMI < 50 ms Communication NAV RAD DB Thiele, ETHZ

39 Use case 1: Change Audio Volume Communication Resource Demand Thiele, ETHZ

40 Use case 2: Lookup Destination Address < 200 ms MMI Communication NAV RAD DB Thiele, ETHZ

41 Use case 2: Lookup Destination Address Thiele, ETHZ

42 Use case 3: Receive TMC Messages MMI < 1000 ms Communication NAV RAD DB Thiele, ETHZ

43 Use case 3: Receive TMC Messages Thiele, ETHZ

44 Proposed Architecture Alternatives (A) 22 MIPS MMI 72 kbps 22 MIPS 57 kbps (B) MMI 113 MIPS 11 MIPS 113 MIPS 11 MIPS NAV 72 kbps RAD NAV RAD (C) 260 MIPS 72 kbps 22 MIPS (D) 113 MIPS 72 kbps 130 MIPS (E) 260 MIPS RAD MMI NAV RAD MMI NAV MMI RAD NAV Thiele, ETHZ

45 Step 1: Environment (Event Steams) Event Stream Model e.g. Address Lookup (1 event / sec) [events] 1 α u α l 1 [s] Thiele, ETHZ

46 Step 1: Architectural Elements Event Stream Model e.g. Address Lookup (1 event / sec) [events] α u 1 α l Resource Model e.g. unloaded RISC CPU (113 MIPS) [MIPS] [s] β l =β u 1 [s] Thiele, ETHZ

47 Step 2: Mapping / Scheduling Rate Monotonic Scheduling (Pre-emptive fixed priority scheduling): Priority 1:Change Volume (p=1/32 s) Priority 2:Address Lookup (p=1 s) Priority 3:Receive TMC (p=6 s) Thiele, ETHZ

48 Step 2: Performance Model Change Volume α CPU1 BUS CPU2 CPU3 MMI NAV RAD β β β β Address Lookup α Receive TMC α MMI NAV RAD Thiele, ETHZ

49 Analysis Design Question 1 How do the proposed system architectures compare in respect to end-to-end delays? Thiele, ETHZ

50 Analysis Design Question 1 End-to-end delays: (A) (B) (C) (D) (E) Vol Key 2 Audio [ms] Vol Vis. 2 Audio [ms] Address Lookup [ms] 0 TMC Decode [ms] Thiele, ETHZ

51 Analysis Design Question 2 How robust is architecture A? Where is the bottleneck of this architecture? (A) 22 MIPS MMI 113 MIPS NAV 72 kbps 11 MIPS RAD Thiele, ETHZ

52 Analysis Design Question 2 TMC delay vs. MMI processor speed: (A) 26.4 MIPS 22 MIPS MMI 113 MIPS NAV 72 kbps 11 MIPS RAD Thiele, ETHZ

53 Analysis Design Question 3 Architecture D is chosen for further investigation. How should the processors be dimensioned? (D) 113 MIPS NAV 72 kbps 130 MIPS RAD MMI Thiele, ETHZ

54 Analysis Design Question 3 d max = 200 d max = MIPS 113 MIPS 72 kbps 33 MIPS 130 MIPS d max = 200 d max = 1000 NAV RAD MMI Thiele, ETHZ

55 Conclusions Realtime Calculus Easy to construct models Evaluation speed is fast and linear to model complexity (~ 1s per evaluation) Needs little information to construct early models (Fits early design cycle very well) Results conservative (may underestimate performance) Thiele, ETHZ