A compositional approach to embedded system performance analysis

Transcription

1 A compositional approach to embedded system performance analysis R. Ernst TU Braunschweig R. Ernst, TU Braunschweig 1 Overview heterogeneous embedded architectures formal performance analysis holistic and flow based a compositional approach to performance analysis example context aware analysis conclusion R. Ernst, TU Braunschweig 5 1

2 Embedded systems - trends Trend 1: higher system integration integration of complete programmable subsystems on a single IC Multiprocessor-Systems-on-Chip (MpSoC) R. Ernst, TU Braunschweig 6 Nexperia example: Viper Setop Box External SDRAM D$ I$ MIPS (PR3940) CPU Memory controller TriMedia (TM32) CPU D$ I$ Interrupt controller Enhanced JTAG Fast PI bus Fast C-Bridge Mem. Mgmt. IF bus TriMedia C-Bridge TriMedia PI bus Clocks IC debug CPU debug Universal serial bus Universal async. receiver/transmitter (UART) ISO UART Reset MIPS bridge MIPS PI bus MIPS C-Bridge High-performance 2D-rendering engine Exp. bus interface unit PCI/XIO I²C IEEE 1394 link layer controller CRC DMA C-bridge MPEG-2 video decoder Adv. image composition Processor Video input processor Memory-based scaler MPEG system proc. Interrupt ctrl. Audio I/O Sony Philips Digital I/O Transport stream DMA General-purpose I/O Synchronous serial interface R. Ernst, TU Braunschweig 7 2

3 Embedded systems - trends - 2 Trend 2: networked systems ubiquitous computing, telecom, automotive, avionics, space,... subsystem subsystem integration integration service service integration integration Image source: Siemens R. Ernst, TU Braunschweig 8 Embedded architectures - trends system function integration reactive and transformative parts function IP, legacy code, new functions component and subsystem reuse (IP) increased design productivity and reduced development cost programmable platforms improved design productivity increased volume examples: network processors, multi-media platforms, automotive platforms, game platforms R. Ernst, TU Braunschweig 9 3

4 Embedded architecture - challenges design specialization increased performance reduced power consumption lower cost and size design flexibility late changes, platforms, reuse HW and SW IP integration result of reuse embedded HW architectures are heterogeneous R. Ernst, TU Braunschweig 10 ES architectures are heterogeneous different processing element types processors, weakly programmable coprocessors, IP components different interconnection networks and communication protocols different memory types different scheduling and synchronization strategies M P M DSP M M P CoP R. Ernst, TU Braunschweig 11 4

5 Heterogeneous architecture: Viper Setop Box External SDRAM D$ I$ MIPS (PR3940) CPU Memory controller TriMedia (TM32) CPU D$ I$ Interrupt controller Enhanced JTAG Fast PI bus Fast C-Bridge Mem. Mgmt. IF bus TriMedia C-Bridge TriMedia PI bus Clocks IC debug CPU debug Universal serial bus Universal async. receiver/transmitter (UART) ISO UART Reset MIPS bridge MIPS PI bus MIPS C-Bridge High-performance 2D-rendering engine Exp. bus interface unit PCI/XIO I²C IEEE 1394 link layer controller CRC DMA C-bridge MPEG-2 video decoder Adv. image composition Processor Video input processor Memory-based scaler MPEG system proc. Interrupt ctrl. Audio I/O Sony Philips Digital I/O Transport stream DMA General-purpose I/O Synchronous serial interface R. Ernst, TU Braunschweig 12 Managing HW architecture complexity development of application programmer interfaces (API) to hide complexity from application programmer and improve portability specialized RTOS to control resource sharing and interfaces complex multi-level HW/SW architecture R. Ernst, TU Braunschweig 13 5

6 Software architecture example software shared mem private private private private pe 1 application RTOS-APIs RTOS drivers application architecture API hardware periphery cache core I/O Int timer timer Bus- CTRL ce 1 layered software architecture with HW dependent SW and API embedded SW is heterogeneous Bus R. Ernst, TU Braunschweig 14 Communication Centric Design communication network as a backbone for systems integration state of the art: off chip: busses w. different protocols and performance levels on chip: Proprietary or standard buses with bridges AMBA, Sonics,... future: multi-stage networks on-chip as well as off-chip (PCI Express) IP CoPro MEM Application B RISC MEM DSP IP communication network VLIW MEM Application A R. Ernst, TU Braunschweig 15 6

7 Subsystem integration - example P 2 P 1 P 3 subsystem 2 Sens CPU M 1 DSP M 2 HW Integration IP 1 M 3 IP 2 subsystem 1 Sens CPU M 1 HW subsystem 1 Com Netw subsystem 2 IP 1 M 3 IP 2 DSP M 2 R. Ernst, TU Braunschweig 16 Communication centric design - key challenges subsystem integration&verification design space exploration and optimization R. Ernst, TU Braunschweig 17 7

8 Integration tasks resource sharing several SW processes mapped to one processing element task scheduling mapping several communications mapped to one communication path communication (bus) scheduling several process data mapped to one memory memory assignment (space & time) interface synthesis synthesizing process communication to target system communication integration verification R. Ernst, TU Braunschweig 18 Integration verification correct implementation of specified function HW/SW co-simulation, verification correct target architecture parameters processor and communication performance adherence to timing requirements no memory over/underflow no run-time dependent dead-locks general design problem challenge to heterogeneous system design R. Ernst, TU Braunschweig 19 8

9 Complex performance objectives and constraints C P sens. C P detc C P ctrl C P act. C application application MEM RTOS-APIs RTOS drivers RTOS-APIs RTOS drivers MEM Crash Sensor cache I/O core int timer timer bus- CTRL system bus timer timer bus- CTRL core int I/O cache Actuator Release Airbag Reaction time of airbag after crash? t crash + t sens + t csens + t detc + t fbus + t ctrl + t cact + t act + t airbag = = = = = physical delay t com t API t API + t drv + t process t physical delay drv t API t drv + t com + t process + t com + t API + t drv + t API R. Ernst, TU Braunschweig 20 Complex run-time interdependencies Sens CPU M 1 HW Com Netw IP 1 M 3 IP 2 DSP M 2 run-time dependencies of independent components via communication influence on timing and power R. Ernst, TU Braunschweig 21 9

10 Interdependency example complex non-functional interdependencies complex system corner cases min execution time high bus load max execution time low bus load P 1 t bc1 t wc1 M 1 CPU 1 communication network R. Ernst, TU Braunschweig 22 Heterogeneous resource sharing - example FCFS scheduling static priority scheduling CoPro RISC MEM DSP TDMA scheduling IP com. netw. MEM IP VLIW MEM static execution order scheduling proprietary (abstract info) earliest deadline first scheduling R. Ernst, TU Braunschweig 23 10

11 Performance verification - state of the art current approach: target architecture co-simulation combines functional and performance validation reuse component validation pattern for system integration and function test reuse application benchmarks for target architecture function validation visualization of system execution extensive simulation run times to include many test cases R. Ernst, TU Braunschweig 24 Co-simulation limitations identification of system performance corner cases different from component performance corner cases target architecture behavior unknown to the application function developer (cp. functional HW test) test case definition and selection? analysis of target architecture confusing variety of run-time interdependencies data dependent transient run-time effects mixed in co-simulation limited support of design space exploration debugging challenge inclusion of incomplete application specifications additional performance models required R. Ernst, TU Braunschweig 25 11

12 Alternatives? conservative design install independency in resource sharing example: fixed execution time slots TDMA formal performance analysis R. Ernst, TU Braunschweig 26 Formal performance analysis formal techniques known for individual components and subsystems (RMS, static scheduling etc.) heterogeneity is problem R. Ernst, TU Braunschweig 29 12

13 Performance model structure IP M model type system model influenced by communication pattern shared memory access environment model M P M P activation P 1 P 2 M component & communication execution model resource sharing strategy process activation component state (caches) P 1 process execution model execution path data dependent path execution arch. dependent communication data & arch. dep. R. Ernst, TU Braunschweig 30 System performance analysis approaches global approach analysis scope extension to several subsystems flow based hierachical approach global flow analysis combined with local scheduling analysis R. Ernst, TU Braunschweig 31 13

14 Analysis scope extension coherent analysis ( holistic approach) example: Tindell 94, Pop/Eles (DATE 2000, DAC 2002, ): TDMA + static priority automotive applications static priority process scheduling static priority queueing T: Transmitter process queue P 2 P 1 T TTP bus interface RTOS P 3 P 4 D RTOS TTP bus interface TTP bus (TDMA) problem: scalability R. Ernst, TU Braunschweig 32 Hierarchical approach independently scheduled subsystems are coupled by data flow SB 1 P 1 SB 2 P 3 P 2 P 4 scheduling SB 1 scheduling SB 2 subsystems coupled by stream of data interpreted as activating events coupling corresponds to event propagation R. Ernst, TU Braunschweig 33 14

15 Event propagation and analysis principle environment model local analysis derive output event model map to input event model until convergence or non-schedulability R. Ernst, TU Braunschweig 34 Flow based hierarchical approaches event model generalization for a set of scheduling strategies arrival and service curves Chakraborty/Thiele/Gries/Künzli new analysis approaches needed, e.g. Baruah used for network processor design event stream model adaptation use abstract interface stream properties to couple local analysis used e.g. for automotive software R. Ernst, TU Braunschweig 35 15

16 Generalized event model incoming events stream is integrated over time intervals and captured in arrival curves event consumption is captured in service curves 2 curves each for upper and lower bounds (interval) upper and lower bounds linearly approximated for analyis R. Ernst, TU Braunschweig 36 Load analysis with interval event model Load analyis: Addition propagation of computation and load intervals - min/max algebra e.g. buffer size: difference between input load and processed events HW and SW resources resource bounds input stream bounds source: L. Thiele, ETH Zurich remaining resources processed packet streams R. Ernst, TU Braunschweig 37 L. Thiele, ETH Zurich 16

17 Compositional Approach (Ernst et al.) observation: real-time analysis assumes similar event models at input t e1 t e2 t e3 periodic event stream t p t p periodic event streams with jitter periodic event streams with burst t e1 t e2 t e3 t p t p t e1 t e2 t e3 t en t en+1 t min sporadic events with minimum event separation t int t e1 t e2 sporadic events with bursts comparable event models appear at output volume of generated events is fixed or interval (data dependent) R. Ernst, TU Braunschweig 38 static execution order RTA event model examples periodic periodic w. jitter Jitter: fixed part (scheduling) + variable part (data dependency) sporadic sporadic w. jitter static priority periodic periodic w. jitter and burst sporadic sporadic w. jitter and burst time driven scheduling: TDMA, round robin adds jitter to any model R. Ernst, TU Braunschweig 39 17

18 Example: Static priority with arbitrary deadlines complex execution sequence - may create output bursts found in communication scheduling and multiprocessing P 1 T 1 P 2 T 2 T 2 T 2 T 2 P 3 priority busy period analysis solution e.g. by Lehoczky R. Ernst, TU Braunschweig 40 Few stream models can be derived n act (t) no. of activating events in time t burst can be simplified and modeled as jitter greater period with min. event distance R. Ernst, TU Braunschweig 41 18

19 Event stream model adaptation composition requires model adaptation adaptation for compatible input and output event models simple mathematical transformation to adapt analysis Event Model InterFace (EMIF) no added function, no run-time effect adaptation for non-compatible input and output event models insert Event Adaptation Function (EAF) to transform models EAF describes interface buffer function shows that buffer is required to couple subsystems R. Ernst, TU Braunschweig 42 Event Model Interface Classification periodic burst T T T=T, length t=t, (b) b=1 = 1 jitter T=T, = J=0 0 periodic with burst b T b t t t = t t = T sporadic x t x t x t periodic with jitter T T J J J t = T - J lossless EMIF EMIF to less expressive model R. Ernst, TU Braunschweig 43 19

20 Using EMIFs and EAFs EAF buffer required Periodic Periodic with Burst Periodic with Jitter Sporadic upper bound only R. Ernst, TU Braunschweig 44 subsystem 1 Example revisited non-functional dependency cycle com. netw. Distortion subsystem 2 R. Ernst, TU Braunschweig 45 20

21 Sens CPU M 1 sporadic sporadic burst EMIF EMIF EMIF HW EMIF sporadic com. netw. C 1 C 3 C 2 burst-based network analysis EMIF EMIF w/ EAF periodic periodic IP 1 M 3 IP 2 DSP R. Ernst, TU Braunschweig 46 M 2 Dependency cycle activation by RTOS simple periodic Sens sporadic w/ jitter preemption P1 P3 CPU periodic w/ burst EMIF w/ EAF resynchronization reduces HWjitter EMIF simple periodic C1 interference C2 NoC com. network R. Ernst, TU Braunschweig 47 21

22 t (P 1 )= 250 µs t (P 3 )= 10 µs simple sporadic f max =1,7kHz, s=8kb Sens 8kB 32 ( ) byte CPU s=3kb simple periodic f=20khz M 1 periodic w/ burst HW sporadic w/ jitter EMIF EMIF w/ EAF 3kB 24 ( ) byte simple sporadic periodic w/ burst com. network NoC C 1 C 3 C 2 1kB 1 ( ) byte periodic w/ jitter periodic f=140khz, s=1kb EMIF w/ EAF periodic IP 1 M 3 IP 2 DSP R. Ernst, TU Braunschweig 48 M 2 Results 39 R. Ernst, TU Braunschweig 49 22

23 Application model compatibility stream model represents exact data volume keeps causality for application model activation required for AND activation, e.g. data flow graphs otherwise infinite buffers or starvation 1 P P 1 P 2 P 1 P CPU1 CPU2 CPU1 CPU2 not needed for process systems with OR activation or time driven activation R. Ernst, TU Braunschweig 50 System contexts another stream property partial event order is kept application: tagged token (SPI model) to take system contexts into account example set top box R. Ernst, TU Braunschweig 51 23

24 Context exploitation: Set top box RF system bus decryption unit hard-disk R. Ernst, TU Braunschweig 52 Context exploitation: Set top box mux MPEG-2 IP-traffic RF decryption unit hard-disk scenario 1: record video + watch movie + download file via IP R. Ernst, TU Braunschweig 53 24

25 MPEG stream modeling stream properties I, B, P frame types of different data volume encoding with the following constraint on frame types Min 2 I out of 12 Min 2 P out of 12 Min 6 B out of 12 Max 4 I out of 12 Max 4 P out of 12 Max 8 B out of 12 stream coding set of constraints on the sequence of tagged tokens R. Ernst, TU Braunschweig 54 intra event stream context Event stream contexts data volume and execution time depend on frame types and frame sequence inter event stream context bus load and response times depend on relative phase of streams inter + intra event stream contexts merged streams on bus have variable order solutions available for cyclo static streams (Chen/Mok) and inter event stream contexts only (Tindell), extended to constrained sequences and combinations R. Ernst, TU Braunschweig 55 25

26 Response time impact mux IP video streams are multiplexed and have higher priority than IP 118 I I I I I I I w/o context t respip = 920 I t I I I I P w context t respip =690 P t response times for static priority bus arbitration R. Ernst, TU Braunschweig 56 Analysis improvement due to intra event stream contexts t t resp,max resp,max w context w/o context R. Ernst, TU Braunschweig 57 26

27 Set top box scenario 2 Encrypted MPEG-2 Decrypted MPEG-2 IP-traffic RF decryption unit hard-disk scenario 2: decript video + download file via IP R. Ernst, TU Braunschweig 58 Response time impact enc dec IP 100 I enc I dec I enc I dec 170 t transaction period = 100 I enc 50 I dec 140 enc and dec streams are coupled by decryption unit execution time R. Ernst, TU Braunschweig 59 I enc I dec t 27

28 Analysis improvement due to inter event stream contexts t t resp,max resp,max w context w/o context R. Ernst, TU Braunschweig 60 Analysis improvement due to both intra and inter event stream contexts t t resp,max resp,max w context w/o context R. Ernst, TU Braunschweig 61 28

29 Acknowledgement The following persons made major contributions to this work Jörn Braam J. Bhavani Rafik Henia Marek Jersak Razvan Racu Kai Richter R. Ernst, TU Braunschweig 62 Conclusion systems integration is key ES design problem performance verification is key integration problem many hidden performance problems not reflected in system function performance verification currently primarily based on simulation risky and time consuming presented compositional analysis based on abstract event flow models event flow models enable analysis of complex situations with feedback and contexts work applied in several ongoing industry cooperations (SpeAC, FlexFilm, automotive SW, ) R. Ernst, TU Braunschweig 63 29

30 see: Literature R. Ernst, TU Braunschweig 64 30