Embedded Systems Design: Optimization Challenges. Paul Pop Embedded Systems Lab (ESLAB) Linköping University, Sweden

Transcription

1 of /4 4 Embedded Systems Design: Optimization Challenges Paul Pop Embedded Systems Lab (ESLAB) Linköping University, Sweden

2 Outline! Embedded systems " Example area: automotive electronics " Embedded systems design " Optimization problems " Fault-tolerant mapping and scheduling " Voltage scaling " Communication delay analysis " Assessment and message of /4 4

3 3 of 3/4 4 Embedded Systems General purpose systems Embedded systems Microprocessor market shares 99% %

4 4 of 4/4 4 Example Area: Automotive Electronics " What is automotive electronics? " Vehicle functions implemented with electronics " Body electronics " System electronics: chassis, engine " Information/entertainment

5 5 of 5/4 4 Automotive Electronics Market Size Cost of Electronics / Car ($) 6: 5% of the total cost of a car will be electronics Market ($billions) % of future innovations in vehicles: based on electronic embedded systems

6 Automotive Electronics Platform Example Source: Expanding automotive electronic systems, IEEE Computer, Jan. 6 of 6/4 4

7 Outline " Embedded systems " Example area: automotive electronics! Embedded systems design " Optimization problems " Fault-tolerant mapping and scheduling " Voltage scaling " Communication delay analysis " Assessment and message 7 of 7/4 4

8 Embedded Systems Design "Growing complexity "Constraints "Time, energy, size "Cost, time-to-market "Safety, reliability System model System platform Estimation: exec. time System-level design tasks " Mapping and scheduling " Voltage scaling "Heterogeneous "Hardware components "Comm. protocols Model of system implementation Analysis Software synthesis Hardware synthesis " Communication delay analysis 8 of 8/4 4

9 Embedded System Design, Cont. " Goal: automated design optimization techniques " Successfully manage the complexity of embedded systems " Meet the constraints imposed by the application domain " Shorten the time-to-market " Reduce development and manufacturing costs Optimization: the key to successful design 9 of 9/4 4

10 Outline " Embedded systems " Example area: automotive electronics " Embedded systems design! Optimization problems " Fault-tolerant mapping and scheduling " Voltage scaling " Communication delay analysis " Assessment and message of /4 4

11 Optimization Problems. Mapping and scheduling. Mapping to minimize communication. Mapping and scheduling.3 Fault-tolerant mapping and scheduling. Voltage scaling. Continuous voltage scaling. Discrete voltage scaling 3. Communication delay analysis of /4 4

12 of /4 4 Problem #.: Mapping #Given " Application: set of interacting processes " Platform: set of nodes P m m 3 m 4 Determine " Mapping of processes to nodes " Such that the communication is minimized N! Assessment " Optimal solutions even for large problem sizes

13 3 of 3/4 4 Problem #.: Mapping and Scheduling #Given " Application: set of interacting processes " Platform: set of nodes " Timing constraints: deadlines Determine " Mapping of processes and messages " Schedule tables for processes and messages " Such that the timing constraints are satisfied P m m 3 m 4 N Schedule table N Bus P S S m m 3 m 4 Deadline

14 4 of 4/4 Problem #.:!Assessment " Scheduling is NP-complete even in simpler context " D. Ullman, NP-Complete Scheduling Problems, Journal of Computer Systems Science, volume, pages , 975. " ILP formulation " Can t obtain optimal solutions for large problem sizes " Alternative: divide the problem " Scheduling " Heuristic: List scheduling " Mapping " Simulated annealing " Tabu-search " Problem-specific greedy algorithms

15 5 of 5/4 4 Fault-Tolerant Mapping and Scheduling Transient faults... Processes: Re-execution Schedule and tables replication TDMA bus: TTP Messages: Fault-tolerant Schedule tables protocol

16 6 of 6/4 4 Fault-Tolerance Techniques N P N P P N P P P P P N 3 P Re-execution Replication Re-executed replicas

17 7 of 7/4 4 #Given Problem #.3: Formulation " Application: set of interacting processes " Platform: set of nodes " Timing constraints: deadlines " Fault model: number of transient faults in the system period Determine Application: set of process graphs Fault-model: transient faults " Mapping of processes and messages... " Schedule tables for processes and messages " Fault-tolerance policy assignment " Such that the timing constraints are satisfied Architecture: time-triggered system

18 8 of 8/4 4 Fault-Tolerance Policy Assignment Deadline N P No fault-tolerance: application crashes TTP S S N P Missed TTP S S P m 3 m P N N

19 9 of 9/4 4 Fault-Tolerance Policy Assignment Deadline N P No fault-tolerance: application crashes TTP S S N P Missed P Missed TTP S S m m m 3 m 3 P m 3 m P N N

20 of /4 4 Fault-Tolerance Policy Assignment Deadline N P No fault-tolerance: application crashes TTP S S N P P MetMissed Missed Optimization of fault-tolerance policy assignment TTP S S m m m 3 m 3 P m 3 m P N N

21 of /4 4 Tabu-Search: Policy Assignment & Mapping N P Tabu Wait P Current solution TTP S S S Design transformations P m 3 m P N N

22 of /4 4 Tabu-Search: Policy Assignment & Mapping N P Tabu Wait P Current solution TTP S S S Design transformations N P Tabu Wait P Tabu move & worse than best-so-far TTP S S S m P m 3 m P N N

23 3 of 3/4 4 Tabu-Search: Policy Assignment & Mapping N P Tabu Wait P Current solution TTP S S S Design transformations N P P Tabu Wait P Tabu move & worse better than best-so-far TTP S S m S m P m 3 m P N N

24 4 of 4/4 4 Tabu-Search: Policy Assignment & Mapping N P Tabu Wait P Current solution TTP S S S Design transformations N P P Tabu Wait P Tabu Non-tabu move & better worse than best-so-far TTP S S S m S m P m 3 m P N N

25 5 of 5/4 4 Tabu-Search: Policy Assignment & Mapping N P Tabu Wait P Current solution TTP S S S Design transformations N P P Tabu Wait P Non-tabu Tabu move & & worse better than best-so-far TTP S S S m S m P m 3 m P N N

26 6 of 6/4 4 Tabu-Search: Policy Assignment & Mapping N P P Tabu Wait P Current solution TTP S S S m Design transformations Design transformations N P P Tabu Wait P Non-tabu Tabu move & & worse better than best-so-far TTP S S S m S m P m 3 m P N N

27 Problem #: Voltage Scaling "GSM Phone: "Search "Radio link control "Talking "MP3 Player "Digital Camera: "Take photo "Restore photo Power constraints Battery power Chip power Timing constraints 7 of 7/4 4

28 8 of 8/4 4 Problem #: Voltage Scaling Different voltages: different frequencies Power CPU V dd V bs f τ τ τ 3 f f3 Slack deadline P t Energy/speed trade-offs: varying the voltages τ τ τ 3 deadline t Mapping and scheduling: given (fastest freq.)

29 9 of 9/4 4 Problem #.: Continuous Voltage Scaling #Given " Application: set of interacting processes " Platform: set of nodes, each having supply voltage (V dd ) and body bias voltage (V bs ) inputs " Mapping and schedule table (including timing constraints) Architecture and mapping Schedule table / processor V dd V bs CPU τ CPU τ τ τ 3 Bus τ 5 τ 4 CPU3 V dd V bs V dd V bs P τ τ τ 3 Slack t deadline

30 3 of 3/4 4 Problem #.: Continuous Voltage Scaling Determine " Voltage levels V dd and V bs for each process " Such that system energy is minimized and " Deadlines are satisfied P Height: voltage level Area: energy P Slack τ τ τ 3 deadline τ τ τ 3 deadline t t #Input Output

31 3 of 3/4 4 Problem #.: Continuous Voltage Scaling Determine " Voltage levels V dd and V bs for each process " Such that system energy is minimized and " Deadlines are satisfied! Assessment P " Convex nonlinear problem Height: voltage level τ τ τ 3 Area: energy P Slack τ τ τ 3 deadline t #Input " Polynomial time solvable with an arbitrary good precision " A. Andrei, Overhead-Conscious Voltage Selection for t Dynamic and Leakage Energy Reduction of Time-Constrained Systems, technical deadline report, Linköping University, 4 Output

32 Problem #.: Formulation " Minimize energy " E[τ ] + E[τ ] + E[τ ] + E_OH[τ -τ ] CPU BUS CPU τ Energy due to processes Overhead due to voltage changes τ τ " Such that " T start [τ ] + T exe [τ ] T start [τ ] " T start [τ ] + T exe [τ ] + T oh [τ -τ ] T start [τ ] Precedence relationships " T start [τ ] + T exe [τ ] DL[τ ] Deadlines 3 of 3/4 4

33 33 of 33/4 4 Problem #.: Discrete Voltage Scaling " Problem formulation #Given discrete execution frequencies Processors can operate using a frequency from a fixed discrete set Changing the frequency incurs a delay and an energy penalty Determine the set of frequencies for each task " Such that system energy is minimized and " Deadlines are satisfied P Discrete deadline f f 3 f 3 f f τ f τ τ 3 t

34 34 of 34/4 4 #Given " processor: f {5,, 5} MHz " 3 processes " τ : P={,, 3} mw, dl=ms, NC= cycles " τ : P={,, 3} mw, dl=.5ms, NC= cycles " τ 3: P={5, 5, 35} mw, dl=ms, NC= cycles " Schedule: execution order is τ, τ, τ 3 Determine " For each process, number of clock cycles to be executed at each frequency 3 3 ( c, c, c ),( c, c, c ),( c3, c3, c " such that the energy is minimized Problem #.: Example 3 3 )

35 35 of 35/4 4!Assessment: " Strongly NP-hard problem Problem #.: Example, Cont. " The frequencies are now a set of integers; identical to: " P. De, Complexity of the Discrete Time-Cost Tradeoff Problem for Project Networks, Operations Research, 45():3 36, March 997. " MILP formulation for the optimal solution 3 c i + ci + ci = NCi 3 ci ci ci + + = t 3 f f f starti + ti ti+ start t dl Each task has to execute the given number of cycles i i i i c 3 i ci ci Pi + Pi + P 3 3 i f i Task execution time Precedence constraints + Deadline constraints f f Minimize energy

36 36 of 36/4 4 Embedded Systems Design System model System platform Estimation: exec. time System-level design tasks "Communication protocols Mapped and scheduled model Analysis Software synthesis Hardware synthesis " Communication delay analysis

37 37 of 37/4 4 " FlexRay communication protocol Problem #3: FlexRay Analysis " Becoming de-facto standard in automotive electronics " BMW, DaimlerChrysler, General Motors, Volkswagen, Bosch, Motorola, Philips " Deterministic data transmission, fault-tolerant, high data-rate " Problem #Given Worst-case communication delay " Application: set of interacting processes " Platform: set of nodes connected by FlexRay " Implementation: S Mapping and... schedulingr Determine Communication protocol: FlexRay " Worst-case communication delays for messages

38 38 of 38/4 4 Problem #3: FlexRay Analysis, Cont. Bus cycle Static Dynamic Static Dynamic Generalized Time-division multiple access Statically assigned m m 3 Flexible Time-division multiple access Arrive dynamically m 7 m 4 m 5 m 6 Off-line: Schedule table Off-line: Worstcase analysis

39 39 of 39/4 4 Problem #3: Formulation and Example #Given " FlexRay bus " Length of the static phase " Length of the dynamic phase " Dynamically arriving messages " Priorities Determine for each message " Worst-case communication delay Priority m 4 m 7 m 5 m 6 Analyze this! Static Dynamic m Static Dynamic m Static Dynamic 7 6 m 4 m 5 Fixed size bin Bin covering: two bins

40 " Classic bin covering problem #Given " Set of bins of fixed integer size " Set of items of integer size Determine Problem #3:!Assessment " Maximum number of bins that can be filled with the items! Assessment " Asymptotic fully polynomial time approximation " FlexRay dynamic phase analysis classic bin covering " Bins have an upper limit: size of the dynamic phase " Assessment " Approximation algorithm does not exist Wanted: better solution " MILP formulation feasible up to 6 messages 4 of 4/4 4

41 Outline " Embedded systems " Example area: automotive electronics " Embedded systems design " Optimization problems " Fault-tolerant mapping and scheduling " Voltage scaling " Communication delay analysis! Assessment and message 4 of 4/4 4

42 Message " Optimization " Key to successful embedded systems design " Challenges " Classify the problems " Divide the problem into sub-problems " Formulate the problems " Solve the problems optimally " Fast and accurate heuristics for specific problems 4 of 4/4 4