Real-Time Scheduling and Resource Management

Transcription

1 ARTIST2 Summer School 2008 in Europe Autrans (near Grenoble), France September 8-12, 2008 Real-Time Scheduling and Resource Management Lecturer: Giorgio Buttazzo Full Professor Scuola Superiore Sant Anna 1

2 Outline Importance of scheduling in embedded systems Review of main scheduling algorithms Schedulability analysis Taking into account shared resources Preemptive vs. Non preemptive scheduling Bounding delays and jitter Managing oveloads Design issues: integrating RT and control theory 2 2

3 Software Control Systems processor D/A actuators Environment A/D sensors Task Memory buffer 3

4 Typical task structure buffer <read data> <process data> <write data> <wait for next activation> buffer 4

5 Activation modes Periodic task (time driven) timer A task is automatically activated by the kernel at regular time intervals Task body Aperiodic task (event driven) A task is activated upon the arrival of an event (interrupt or explicit activation) event Task body 5

6 Complex control applications Hierarchical design Many periodic activities running a different rates Many event-driven routines 40 ms 15 ms 1 ms 4 ms sensor motor sensor motor 6

7 Task scheduling When more tasks are ready to execute, the order of execution is decided by the scheduler: READY queue CPU 7

8 Importance of scheduling It affects task response times It affects delay and jitter in control loops It affects execution times (preemptions destroy cache data and prefetch queues) It can be used to cope with overload conditions It can be used to optimize resource usage It can be used to save energy in processors with voltage scaling (energy-aware scheduling) 8

9 Periodic Task Scheduling We have n periodic tasks: {τ 1, τ 2 τ n } τ i (C i, T i, D i ) period relative deadline absolute deadline d i,k Ti Di Ci r i,1 = Φ i r i,k r i,k+1 t di,k Goal Execute all tasks within their deadlines Verify feasibility before runtime r i,k = Φi + (k 1) T i d i,k = r i,k + D i 9

10 Optimal Priority Assignments Rate Monotonic (RM): p i 1/T i (static) D i = T i Deadline Monotonic (DM): p i 1/D i (static) D i T i Earliest Deadline First (EDF): p i 1/d i (dynamic) d i,k = r i,k + D i 10

11 Basic results Assumptions: Independent tasks Φ i = 0 D i = T i In 1973, Liu & Layland proved that a set of n periodic tasks can be feasibly scheduled under RM if n i= 1 C T i i n ( 2 1 n 1) i under EDF if and only if 1 n i= 1 C T i 11

12 Schedulability bound for n U lub ln CPU% RM EDF n 69% 12

13 An unfeasible RM schedule U p = = τ 1 τ deadline miss 13

14 EDF vs. RM Schedule EDF τ 1 τ RM τ τ deadline miss 14

15 Schedulability region A more useful approach is to identify a region in the space of task parameters where the system is schedulable by an algorithm. par2 Infeasible task set feasible region Sensitivity analysis to determine how to change parameters par1 15

16 U Schedulability region EDF RM The U-space n i= 1 n i= 1 U i 1 U i n(2 1/ n 1) U 2 16

17 Schedulability region U 1 1 The U-space C i T i 0.83 τ τ /2 EDF U p = = 0.94 RM U 2 4/

18 The Hyperbolic Bound In 2000, Bini et al. proved that a set of n periodic tasks is schedulable with RM if: n ( U i + 1) 2 i= 1 18

19 U Schedulability region EDF RM The U-space n n i= 1 i= 1 U i 1 U i n(2 1/ n 1) U 2 19

20 Schedulability region U The U-space n n i= 1 U i 1 U i n(2 1/ n 1) EDF i= 1 n ( U i + 1) 2 RM i= 1 U

21 Handling tasks with D < T D i T i τ i r i,k C i d i,k r i,k+1 t Scheduling algorithms Deadline Monotonic: p i 1/D i (static) Earliest Deadline First: p i 1/d i (dynamic) 21

22 How to guarantee feasibility? D i T i τ i r i,k C i d i,k r i,k+1 t Fixed priority: Response Time Analysis (RTA) EDF: Processor Demand Criterion (PDC) 22

23 Response Time Analysis [Audsley, 1990] For each task τ i compute the interference due to higher priority tasks: I i = C k D k < D i Compute its response time as R i = C i + I i Verify if R i D i 23

24 Computing the interference τ k τ i 0 R i Interference of τ k on τ i in the interval [0, R i ]: I = ik R T i k C k Interference of high priority tasks on τ i : i 1 I i = k = 1 R T i k C k 24

25 Computing the response time i 1 Ri = C i + k = 1 R T i k C k Iterative solution: 0 R i = C i R s i = C i i 1 + k = 1 R ( s 1) i T k C k iterate until s R i > R ( s 1) i 25

26 Processor Demand Criterion [Baruah, Howell, Rosier 1990] For checking the existence of a feasibile schedule under EDF In any interval of time, the computation demanded by the task set must be no greater than the available time. t, t > 0, g( t, t ) ( t t )

27 Processor Demand t 1 t 2 The demand in [t 1, t 2 ] is the computation time of those jobs started at or after t 1 with deadline less than or equal to t 2 : g( t, t ) 1 2 = di t r t i 2 1 C i 27

28 Processor Demand For synchronous task sets we can only analyze intervals [0,L] τ i 0 g(0, L) = n i= 1 L D T i i + T i C i L D i T i + D i 2T i + D i 3T i + D i 28 L

29 Processor Demand Test L > 0 n i=1 L D T i i + T i C i L 29

30 Example τ 1 τ 2 g(0, L) L 2 0 L 30

31 Summarizing: RM vs. EDF RM D i = T i Suff.: polynomial LL: ΣU i n(2 1/n 1) HB: Π(U i +1) 2 Exact O(n) pseudo-polynomial RTA i D i T i pseudo-polynomial Response Time Analysis R i D i i 1 Ri = C i + k = 1 R T i k C k EDF polynomial: ΣU i 1 O(n) pseudo-polynomial Processor Demand Analysis L > 0, g(0, L) L 31

32 Handling shared resources Problems caused by mutual exclusion 32

33 Critical sections τ 1 τ 2 wait(s) globlal memory buffer wait(s) x = 3; y = 5; write int x; int y; read a = x+1; b = y+2; signal(s) c = x+y; signal(s) 33

34 Blocking on a semaphore τ 1 τ 2 p 1 > p 2 Δ τ 1 CS CS τ 2 It seems that the maximum blocking time for τ1 is equal to the length of the critical section of τ2, but 34

35 Priority Inversion priority Δ Occurs when a high priority task is blocked by a lower-priority task a for an unbounded interval of time. 35

36 Resource Access Protocols Under fixed priorities Non Preemptive Protocol (NPP) Highest Locker Priority (HLP) Priority Inheritance (PIP) [Sha-Rajkumar-Lehoczcky, 90] Priority Ceiling (PCP) [Sha-Rajkumar-Lehoczcky, 90] Under EDF Non Preemptive Protocol (NPP) Dynamic Priority Inheritance (D-PIP) [Spuri, 98] Dynamic Priority Ceiling (D-PCP) [Chen-Lin, 90] Stack Resource Policy (SRP) [Baker, 90] 36

37 Guarantee when D = T Compute the maximum blocking time for each task Inflate C i by B i Extended LL test: RM i 1 i = k 1 C T k k + C i + T i B i i ( 2 1 /i 1) EDF C C + i 1 k i i + k = 1 Tk Ti B i 1 37

38 Guarantee when D T Under DM a task set is schedulable if i R i D i i 1 Ri = Ci + B i + k = 1 R T i k C k Under EDF a task set is schedulable if U < 1 and i L B i n + k =1 L + T k T k D k C k L 38

39 Non-preemtive scheduling It is a special case of preemptive scheduling where all tasks share a single resource for their entire duration. τ 1 R τ 2 R τ 3 R The max blocking time for task τ i is given by the largest C k among the lowest priority tasks: B i = max{c k : P k < P i } 39

40 Advantages of NP scheduling It reduces runtime overhead Less context switches No semaphores are needed for critical sections It reduces stack size, since no more than one task can be in execution. It preserves program locality, improving the effectiveness of Cache memory Pipeline mechanisms Prefetch queues 40

41 Advantages of NP scheduling As a consequence, task execution times are Smaller More predictable distribution non-preemptive preemptive C min C 41

42 RM Advantages of NP scheduling In fixed priority systems can improve schedulabiilty: 2 4 U = τ τ 2 0 NP-RM deadline miss τ τ

43 Disadvantages of NP scheduling In general, NP scheduling reduces schedulability. The utilization bound under non preemptive scheduling drops to zero: τ 1 τ 2 T 1 C 1 = ε C 2 =T 1 T 2 U = ε C T 1 43

44 Trade-off solutions Tunable Preemptive Systems Compute the longest non-preemptive section that allows a feasible schedule [Baruah-Bertogna, 08]. Allow preemption only in certain points in the code. Task code pp 1 pp 2 pp 1 pp 2 pp 3 pp 3 preemption points 44

45 Handling Jitter & Delay Jitter for an event The maximum time variation in the occurrence of a particular event in two consecutive jobs. In many control applications, delay and jitter can cause instability or jerky behavior 45

46 Definitions Start time delay (Input Latency): INL i,k = s i,k r i,k τ i r i,1 s i,1 r i,2 r i,3 s i,2 s i,3 Start time Jitter (Input Jitter): Absolute: INJ abs = max (s i,k r i,k ) min (s i,k r i,k ) i k Relative: INJ rel = max (s i,k r i,k ) (s i,k-1 r i,k-1 ) i k k 46

47 Definitions Response Time (Output Latency): R i,k = f i,k r i,k τ i r i,1 f i,1 r i,2 r i,3 f i,2 f i,3 Response Time Jitter (Output Jitter): Absolute: RTJ abs = max (f i,k r i,k ) min (f i,k r i,k ) i k Relative: RTJ rel = max (f i,k r i,k ) (f i,k-1 r i,k-1 ) i k k 47

48 Definitions Input-Output Latency: IOL i,k = f i,k s i,k τ i s i,1 f i,1 s i,2 f i,2 s i,3 f i,3 Input-Output Jitter: Absolute: IOJ abs = max (f i,k s i,k ) min (f i,k s i,k ) i k Relative: IOJ rel = max (f i,k s i,k ) (f i,k-1 s i,k-1 ) i k k 48

49 Cause of delays and jitter τ τ task parameters number of tasks total load activation phases scheduling algorithm 49

50 Jitter under RM INJ RTJ IOJ τ τ τ Low priority tasks experience very high delay and jitter 50

51 Jitter under EDF INJ RTJ IOJ τ τ τ For a little increase of RTJ 1, RTJ 3 decreases a lot IOJ = 0 for all the tasks 51

52 Jitter under RM and EDF Normalized Avg. RTJ U = 0.9 N = 10 EDF RM Task number (ordered by increasing periods) 10 52

53 How to handle delay and jitter Two main methods can be used to reduce the effect of delay and jitter: 1. compensate them by proper control actions; 2. reduce them as much as possible. Even when compensation is used, reducing delay and jitter improves system performance Hence we concentrate on reduction methods 53

54 Jitter Reduction methods Three methods can be used to reduce the jitter caused by task interference: 1. Task Splitting 2. Advancing Deadlines 3. Non Preemptive Scheduling 54

55 Reducing Jitter by Task Splitting input part processing part output part The idea is to force input and output parts to execute in a time-triggered fashion, using timers: 55

56 Reducing Jitter by Task Splitting Advantages 1. Jitter is reduced at the minimum possible value; 2. If input and output parts are small, this method is effective for any task, independently of the scheduler and task parameters. 56

57 Reducing Jitter by Task Splitting Disadvantages 1. Extra effort to be implemented; 2. Jitter is reduced at the expense of delay; 3. Input and output parts create extra interference which complicates the analysis and reduces schedulability; 4. Input and output parts may compete and need to be scheduled with some policy. 57

58 Reducing Jitter by Task Splitting Interfering I/O parts τ 1 τ 2 τ 3 τ 4 58

59 Reducing Jitter by Advancing Deadlines The idea is to advance task deadlines to reduce the active window in which jobs can be executed: active window active window active window active window 59

60 Reducing Jitter by Advancing Deadlines Advantages 1. Easy to implement (no special support is required from the OS); 2. No extra interference caused by additional timer interrupts; 3. Both delay and jitter are reduced!! 60

61 Reducing Jitter by Advancing Deadlines Disadvantages 1. Not all tasks can reduce jitter to zero. A further reduction can be achieved by proper offsets, but the analysis requires exponential complexity. 2. Advancing deadlines reduces system schedulability. 61

62 Reducing Jitter by Non Preemption Disabling preemtions a task can be delayed, but once started cannot be interrupted: IOL i,k IOL i,k+1 k IOL i,k = C i IOJ i,k = 0 62

63 Reducing Jitter by Non Preemption Example with 3 tasks τ τ τ 3 63

64 Reducing Jitter by Non Preemption Advantages 1. IOJ i = 0 for all tasks; 2. IOL i = C i for all tasks, simplifying the use of delay compensation techniques; 3. Non preemptive execution also simplifies resource management (there is no need to protect critical sections). 4. Non preemptive execution allows stack sharing. 64

65 Reducing Jitter by Non Preemption Disadvantages 1. Non preemption reduces schedulability (analysis must take blocking times into account); 2. The utilization upper bound drops to zero: U 1 0 U 2 0 C 2 > T 1 C 1 0 T 2 65

66 Scheduling under overload conditions 66

67 RM under overloads U = = 1.25 τ τ τ High priority tasks execute at the proper rate Low priority tasks are completely blocked 67

68 EDF under overloads U = = 1.25 τ τ τ All tasks execute at a slower rate No task is blocked 68

69 EDF under overloads Theorem (Cervin 03) If U > 1, EDF executes tasks with an average period T i = T i U. U = 1.25 τ τ 1 T i 8 T i 10 τ 2 τ τ 2 τ

70 Exploiting control flexibility Relaxing timing constraints The idea is to reduce the load by increasing deadlines and/or periods. Each task must specify a range of values in which its period must be included. Periods are increased during overloads, and reduced when the overload is over. Many control applications allow timing flexibility 70

71 Examples: altimeter reading The smaller the altitude, the higher the acquisition rate: Low rate High rate 71

72 Obstacle avoidance The closer the obstacle, the higher the acquisition rate: us Low rate us High rate 72

73 Engine control Some tasks need to be activated at specific angles of the motor axis: the higher the speed, the higher the rate. ω 73

74 Elastic task model A periodic task τ i is characterized by: (C i, T i-min, T i-max, E i ) Tasks utilizations are treated as elastic springs The resistance of a task to a period variation is controlled by an elastic coefficient E i E i τ i r i T i0 t T i-min T i-max 74

75 Compression algorithm During overloads, utilizations must be compressed to bring the load below a desired value U d. τ 1 τ 2 τ 3 τ 4 U d U τ 1 τ 2 τ 3 τ 4 U d U 75

76 Solution for tasks U = U ( U 0 U ) i io d E E i s then: T = i C U i i 76

77 Solution with constraints Iterative solution O(n 2 ): 0 0 L d L 0 F x x F 0 L d x 77

78 Control design issues Design of control laws Traditional approach Mapping to periodic tasks Schedulability analysis No Feasible? Yes Implementation Run time monitoring Disadvantages Repetitive development process Suboptimal performance Suboptimal use of the resources Meet constraints? Yes No 78

79 Control performance Performance Performance as a function of periods T 2 T 1 79

80 T 2 Sensitivity Analysis T 1 80 Feasible region

81 RT & Control codesign Performance T 2 T 1 81

82 Codesign as optimization Generic control law System performance characterization Sampling period Delay Jitter Performance Resource constraints characterization Optimization process T 2 Task parameters T 1 82

83 Conclusions When designing complex embedded systems: 1. Split your system in components, follow a modular design, with hierarchical control levels with precise interface: sensor motor sensor motor 83

84 processor Conclusions 2. Organize software as a set of control tasks with precise timing and resource constraints: D/A actuators Environment A/D sensors

85 Conclusions 3. Estimate worst-case computation times of tasks, using specific tools and testing. 4. Select an appropriate scheduling algorithm and a suitable resource access protocol. 5. Estimate maximum blocking times due non preemptive sections or mutually exclusive resources. 6. Apply schedulability analysis to verify feasibility.

86 Conclusions 7. If possible, use sensitivity analysis and integrate real-time with control issues at early design stages. 8. Exploit system flexibility defining admissible ranges of parameters to cope with overloads. 9. Perform extensive testing and simulation at each implementation step under worst-case scenarios.