Temperature-Aware Analysis and Scheduling

Transcription

1 Temperature-Aware Analysis and Scheduling Lothar Thiele, Pratyush Kumar

2 Overview! Introduction! Power and Temperature Models! Analysis Real-time Analysis Worst-case Temperature Analysis! Scheduling Stop-and-go Shapers! Embedding into Design Flow 2

3 Power Wall Clock Speed and Power Consumption for Intel x86 Processors [Hennessy, Patterson: HW Interface] 3

4 Thermal Issues of Processing Systems 48-Core Intel SCC platform [Loh: 3D-Stacked Memory Architectures for Multi-Core Processors, 2008] 4

5 Problem Statement Timely behavior is important in many embedded systems: tasks must finish execution within specified deadlines examples: media processing, automotive, avionics Thermal wall: recognized as most significant barrier towards high performance high chip temperatures may lead to long-term reliability concerns and short-term functional errors [Transmeta] Thermal and real-time objectives must be considered simultaneously 5

6 Some Solutions! VLSI design and cooling solutions Thermal-aware design, materials, reduce leakage and switching,... Use better heat sinks, fans, air cooling, liquid cooling! Thermal Management Voltage (and frequency) scaling: Reduce supply voltage and slow down the processor Stop-go execution: Completely turn off components to allow for cooling (clock gating, execution unit throttling) Migration of tasks from hot to cool areas All these techniques can be applied statically or dynamically, and may or may not use temperature sensors (automatic control) Scheduling of jobs and DTM techniques affect both, timeliness and thermal properties. 6

7 Some Interesting Problems! What is the most critical event sequence in terms of maximal chip temperature?! How can we simultaneously guarantee timing and temperature?! What are possible scheduling techniques with low overhead (no temperature sensors, simple control)?! What are suitable temperature-aware mapping schemes for multi-processors? 7

8 Overview! Introduction! Power and Temperature Models! Analysis Real-time Analysis Worst-case Temperature Analysis! Scheduling Stop-and-go Shapers! Embedding into Design Flow 8

9 Single Power Source Model! Frequently used power model for constant voltage silicon chip single power source active processing idle mode temperature-dependent leakage 9

10 Single Power Source Model! Frequently used temperature model silicon chip cooling G I P V T C V 0 T amb power parameters thermal conductance 10 thermal capacity environment temperature

11 Single Power Source Model! Explicit solution:! Explicit solution based on a linear system view: impulse response 11

12 Example active state: dynamic and static (leakage) power temperature increase: based on linear thermal model 12

13 Example idle state: static (leakage) power temperature decrease: based on linear thermal model 13

14 Example peak temperature 14

15 Multi Source Models!!! A computer architecture is not a single power source (gates, arithmetic units, cache, interfaces, ) Packages are complex physical structures Future architectures are multi-core and multi-processors [Intel SCC] [Wei Huang: Hotspot/PhD] [Zanini: Niagara core] 15

16 Multi Source Models! Linear system model: [Atienza 2007] 16

17 Multi Source Models! Explicit solution: impulse response matrix h ij (t) corresponds to impulse response between power source j and temperature location i Construction of impulse response matrix through coordinate transformations. 17

18 Some properties! The self-impulse response h ii (t) is always monotonically decreasing (can be proven through diagonalization of A): temperature rises with power at same location without delay temperature rises with power at some other location after delay 18

19 Where do the parameters come from? application Power / Performance Simulator Temperature Simulator power models of HW components FE modeling of physical structure! Low-level power/ performance simulation/ emulation: Software: [Benini, 2005], [Brooks, 2000] Hardware: [Atienza, 2007]! Temperature simulation: HotSpot: [Huang, 2006] 3DICE: [Sridhar, 2010]! There are other possibilities as well, e.g. model identification and reduction. 19

20 Extensions! Many extension and refinements have been described Voltage and speed scaling Nonlinear models: temperature dependent thermal conductance leads to quadratic differential equation Refined models of temperature and voltage dependent dynamic and static power consumption Other cooling schemes, such as liquid cooling! This presentation: only linear (and quadratic) models. 20

21 Overview! Introduction! Power and Temperature Models! Analysis Real-time Analysis Worst-case Temperature Analysis! Scheduling Stop-and-go Shapers! Embedding into Design Flow 21

22 Typical Scenario dataflow network arbitration services multiprocessor platform 22

23 Modular System Composition CPU BUS DSP server FP TDMA componentbased analysis FP TDMA 23

24 How do we model time, event streams, computation and communication, resource sharing? 24

25 Abstraction Principles! Event-based representations untimed FSM Petri Net timed timed automaton (TA) 25

26 Abstraction Principles! Interval-based representations d 2.5 t [ms] t events α α P J pjd 2.5 Δ [ms] arrival curve 26

27 Time Interval Representations! Real-Time Calculus can be regarded as a worst-case/ best-case variant of classical queuing theory. It is a formal method for the analysis of distributed real-time embedded systems.! Related Work: Min-Plus Algebra: F. Baccelli, G. Cohen, G. J. Olster, and J. P. Quadrat, Synchronization and Linearity --- An Algebra for Discrete Event Systems, Wiley, New York, Network Calculus: J.-Y. Le Boudec and P. Thiran, Network Calculus - A Theory of Deterministic Queuing Systems for the Internet, Lecture Notes in Computer Science, vol. 2050, Springer Verlag, Adversarial Queuing Theory [Andrews, Borodin, Kleinberg, Leighton, 1996] 27

28 Load Model (Environment) Event Stream events number of events in in t=[ ] ms 2.5 t [ms] Arrival Curve α demand α maximum / minimum arriving demand in any interval of length 2.5 ms 2.5 α Δ [ms] 28

29 Service Model (Resources) Resource Availability availability available service in t=[ ] ms 2.5 t [ms] Service Curves [β l, β u ] service β β maximum/minimum available service in any interval of length 2.5 ms 2.5 Δ [ms] 29

30 Processing Model (HW/SW) HW/SW Components Processing semantics and functionality of HW/SW tasks HW/SW Task t Abstract Components β Δ α α RTC 30 Predicate Ψ

31 Greedy Processing Component Behavioral Description Component is triggered by incoming events. GPC A fully preemptable task is instantiated at every event arrival to process the incoming event. Active tasks are processed in a greedy fashion in FIFO order. Processing is restricted by the availability of resources. 31

32 System Composition CPU BUS DSP RM TDMA How to interconnect service? shaper Scheduling! GPC GPC GSC GPC GPC GPC 32

33 System Composition Load Model Service Model Processing Model CPU BUS DSP RM TDMA TDMA GPC GPC GSC GPC GPC GPC 33

34 Greedy Processing Component Behavioral Description Component is triggered by incoming events. GPC A fully preemptable task is instantiated at every event arrival to process the incoming event. Active tasks are processed in a greedy fashion in FIFO order. Processing is restricted by the availability of resources. 34

35 Greedy Processing Component (GPC) R(s, t): arriving workload request in [s, t) C(s, t): resource availability in [s, t) Q(s, t): computation time = processed workload in [s, t) If the input buffer is empty at time s, then C(s,t) Q(s, t) power P(s, t) R(s,t) GPC R (s,t) = Q(s, t) C (s,t) = C(s, t) Q(s, t) 35

36 Abstract Representation! Formalization of abstraction: GPC 36

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40 rate function: 40

41 Abstract Representation! Formalization of abstraction: temperature?? power?? GPC! Abstract computing time: 41

42 Given bound on task arrivals α, then all feasible accumulated computing times are bounded by γ active mode idle mode 42

43 System Composition Load Model Service Model Processing Model CPU BUS DSP RM TDMA TDMA GPC GPC GSC GPC GPC GPC 43

44 Delay and Backlog maximum end-to-end delay D accumulated maximum backlog B end-to-end delay D GPC 1 GPC 2 GPC n 44

45 Overview! Introduction! Power and Temperature Models! Analysis Real-time Analysis Worst-case Temperature Analysis! Scheduling Stop-and-go Shapers! Embedding into Design Flow 45

46 Can we determine worst case temperatures in a compositional framework? 46

47 Given a bound on workload arrivals (arrival curves) a computation model (from workload to task executions) a power model (from task executions to power) a temperature model (from power to temperature) What is the worst-case task arrival sequence that leads to maximal peak temperature? 47

48 A Simple Example bound on event arrivals period: 120 ms jitter: 240 ms interarrival: 30 ms workload model execution time: 30ms 48

49 A Simple Example bound on event arrivals period: 120 ms jitter: 240 ms interarrival: 30 ms workload model execution time: 30ms peak temperatures average workload of tasks (25%): 342.5K random trace (500 s): K reasonable heuristic: K worst case: K 49

50 A Simple Example heuristic worst case 50

51 Sequence of Results Given general thermal model (T: temperature, S: execution rate of processing device): Sequence of partial results: Monotonicity Property Shift Property Worst-case Computing Time Tightness Error Bounds 51

52 Shift Property If H(S, T) satisfies a certain condition (lengthy ), then S(t) S(t) S 2 S 2 S 1 S 1 s t s t All major power/temperature model satisfy this condition, e.g. simple active/idle model, linear or quadratic model with continuous speed, multi-source model (for self-heating). 52

53 Worst-case Computing Time 53

54 Worst-case Computing Time reverse time rate function: maximal temperature 54

55 How large should τ be?! For the linear active-idle model: If the observation time τ satisfies steady-state active mode steady-state idle mode precision and the initial temperature is, then 55

56 A Simple Example bound on event arrivals period: 120 ms jitter: 240 ms interarrival: 30 ms workload model execution time: 30ms peak temperatures average workload of tasks (25%): 342.5K random trace (500 s): K reasonable heuristic: K worst case: K 56

57 A Simple Example 57

58 A Video Stream Example 58

59 A Video Stream Example 100 random simulations worst case peak temperature 59

60 not schedulable under EDF schedulable under EDF change task arrival of video 60

61 Multiprocessor Scenario! MPEG-2 decoding: Picture-in-picture application high resolution Output Device input rate low resolution constant read rate 61

62 Multiprocessor Scenario t Δ 62

63 Multiprocessor Scenario! Model Calibration: SimpleScalar Simulation 1.3 GHz 3 GHz 8Mbps 576 macrobl macrobl GHz 1 frame 2 frames frames/s

64 Multiprocessor Scenario

65 Multiprocessor Scenario Time/Space questions: We know how to do that Do buffers overflow? Output Device Do buffers overflow or underflow? 65

66 Multiprocessor Scenario Temperature question Maximal Temperature? Output Device 66

67 Analysis Results t [ms] 67

68 Multiprocessor Scenario 68

69 Generalizations! So far: no heat exchange between processors and/or cores.! Extensions towards heat transfer are necessary. Intel SCC 69

70 Overview! Introduction! Power and Temperature Models! Analysis Real-time Analysis Worst-case Temperature Analysis! Scheduling Stop-and-go Shapers! Embedding into Design Flow 70

71 How to execute a Directed Acyclic Graph (DAG) on a thermally constrained system while minimizing the makespan? 71

72 Scenario 72

73 Scenario 73

74 Strategy Active/Idle Scheduling 74

75 Strategy Mapping problem well-studied. Heuristics are commonly studied and employed. Here we use a variant of HEFT (Heterogeneous- Earliest-Finish-Time) focus now 75

76 Starting Point Classical Monotonicity 76

77 Now Thermal Monotonicity Proof is based on data flow monotonicity monotonicity of temperature shift property Leads to optimal idle time scheduling 77

78 What is the Target Temperature? 78

79 Using Temperature Sensors 79

80 Mapping! Mapping heuristics for DAG scheduling is a mature topic! Try to make use of classical results (HEFT (Heterogeneous-Earliest-Finish-Time)! Given the monotonicity principle of the thermallyconstrained system we retain the DAG property of the thermal-aware system modify parameters of the DAG to represent thermal behavior! Not the subject of this presentation. Just some examples to see that there are non-intuitive results if you combine real-time and thermal constraints. 80

81 Example 1: FFT Characteristics: Two processors, but P1 is twice as fast as P2. The required idling time changes the effective execution time of tasks on processors. task graph slower, but balanced faster, but not balanced 81

82 Example 2: LU Characteristics: Two equal processors, but large communication time Communication can happen while the processor is cooling and thus the effective communication delay can be lower. task graph optimized without temperature 82 optimized with temperature

83 Overview! Introduction! Power and Temperature Models! Analysis Real-time Analysis Worst-case Temperature Analysis! Scheduling Stop-and-go Shapers! Embedding into Design Flow 83

84 Dynamic Thermal Management (DTM) DTM aims at managing chip temperatures using voltage/frequency scaling (DVS) decreasing headroom for voltage scaling, can t reduce leakage power migration of tasks from hot to cool areas needs complex run-time software support, only for multicore systems turning off components (clock gating, execution unit throttling) Problem statement: Design a Dynamic Thermal Management (DTM) policy, that chooses the mode of the processor (active or idle) such that all jobs complete within their deadlines, and the peak temperature of the system is minimized. 84

85 Problem Statement active state: dynamic and static (leakage) power temperature increase: based on linear thermal model 85

86 Problem Statement idle state: static (leakage) power temperature decrease: based on linear thermal model 86

87 Problem Statement peak temperature: to be minimized 87

88 Problem Statement active-idle DTM scheme peak temperature corresponding temperature 88

89 Problem Statement deadline D : to be satisfied active-idle DTM scheme peak temperature corresponding temperature 89

90 Problem Statement How to choose an optimal active-idle schedule? How to dynamically adapt the schedule (non-deterministic task arrival times)? Is the run-time overhead reasonable? 90

91 Cool Shaper Processor DTM-enabled Processor 91

92 Cool Shaper DTM-enabled Processor Processor non-deterministic task streams with bounded variability and relative deadlines deadline D worst case execution time t 92

93 Cool Shaper DTM-enabled Processor Processor 2 non-deterministic task streams with bounded variability and relative deadlines In no time interval of length, task stream demands more than time units computation time. 93

94 Cool Shaper Processor bounds the workload of the processor tasks not delayed more than necessary 94

95 Greedy Traffic Shaper! Access Shaper delays access requests such that the resulting access pattern conforms to a given specification! Greedy Access Shaper no access request gets delayed any longer than necessary σ 95

96 Modeling of Greedy Shapers Greedy Shaper σ t Abstract Greedy Shaper α α σ Δ 96

97 Cool Shaper Processor bounds the workload of the processor tasks not delayed more than necessary In no time interval of length, the processor has to work longer than time units. 97

98 Cool Shaper Processor bounds the workload of the processor tasks not delayed more than necessary In no time interval of length, the processor has to work longer than time units. deadline 98

99 Cool Shaper - Properties Processor no temperature sensor needed minimal temperature under any linear thermal model with decreasing impulse response deadline guarantee and adaptive if workload for a task or task density smaller than upper bound -> faster processing optimality proof and efficient run-time implementation within the class of leaky bucket shapers switching overhead (time and power) can be considered 99

100 Theory task arrival characterization use arrival curve compositional delay analysis Delay-Theorem: deadline guarantee (network calculus [Cruz]) (real-time calculus [Thiele]) maximum delay GPC maximum delay 100

101 Theory task arrival characterization use arrival curve compositional delay analysis Delay-Theorem: deadline guarantee (network calculus [Cruz]) temperature guarantee Monotonicity-Theorem T T (analysis [Rai, DATE 11]) (real-time calculus [Thiele]) shaper optimality Optimality-Theorem: (based on leaky bucket) minimal peak temperature 101

102 Temperature Guarantee and Leaky Bucket! From the w.c. temperature analysis: :! Simple shaper implementation: Leaky bucket shaper Cascading 102

103 Optimality : 103

104 Theory task arrival characterization use arrival curve compositional delay analysis Delay-Theorem: deadline guarantee (network calculus [Cruz]) temperature guarantee Monotonicity-Theorem T T (analysis [Rai, DATE 11]) (real-time calculus [Thiele]) shaper optimality Optimality-Theorem: (based on leaky bucket) minimal peak temperature consider overhead multiple tasks 104 (demand bound func. [Baruah])

105 Experimental Results (I)! Thermal parameters taken from [Skadron, ISCA 03].! Video decode application with video, audio and network sub-tasks.! Effect of shaping: T max : 346K 338K Execution time of video application can be increased by 40% with T max 346K 105

106 Experimental Results (II)! Choice of optimal switching granularity: explore trade-off between switching overhead and loss in optimality maximal active interval 106

107 Experimental Results (II)! Choice of optimal switching granularity: explore trade-off between switching overhead and loss in optimality maximal active interval! Random task set: with shaping, a higher utilization can be supported at the cost of (almost) linearly increasing peak temperature without cool shaper with cool shaper average utilization 107

108 Related Work! Mainly considering DVS, most results are limited in the task-model (statically given trace, periodic tasks).! This is limiting because job arrivals can show variability such as a periodic task with jitter can exhibit bursts at unknown points.! Examples: Bansal et al [FOCS 04]: set speed of a processor under given thermal constraints Skadron et al [HPCA 02], Wang et al [ RTSS 06] : set speed of a processor using feedback control based on temperature sensors Chen et al [RTAS 09]: set the speed of a processor to tasks for a given set of periodically repeating tasks Cho et al [ICS 07]: system-level techniques such as core-hopping to reduce temperature 108

109 Overview! Introduction! Power and Temperature Models! Analysis Real-time Analysis Worst-case Temperature Analysis! Scheduling Stop-and-go Shapers! Embedding into Design Flow 109

110 Integration of Thermal Analysis! Distributed Operation Layer (DOL)! Goal: Automatically generate an optimized mapping of a parallel application onto MPSoC high-level analysis calibration 110

111 Calibration Tool Chain Sample Mappings Software Synthesis Low-Level Power/ Timing Simulator Thermal Architecture Analysis Execution trace Timing characterization Power characterization Thermal platform model: conductivity matrix capacitance matrix Timing Parameters Thermal Parameters 111

112 High-level Thermal Analysis/Simulation Thermal Platform Model (conductance/capacitance matrix) 112

113 Acknowledgement! Co-workers: Jian-Jia Chen, Iuliana Bacivarov, Devendra Rai, Lars Schor, Pratyush Kumar, Hoeseok Yang! Funding: EU-ARTISTDESIGN, EU-EURETILE, EU-PRO3D,! Further Information: