Thermal Scheduling SImulator for Chip Multiprocessors

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1 TSIC: Thermal Scheduling SImulator for Chip Multiprocessors Kyriakos Stavrou Pedro Trancoso CASPER group Department of Computer Science University Of Cyprus The CASPER group: Computer Architecture System Performance Evaluation Research

2 Outline Temperature problems and TAS TSIC & TAS Related work Thermal Model Thermal Aware Scheduling TSIC: Thermal Scheduling Simulator for CMPs Preliminary Results Work in progress

3 Temperature induced problems Modern microprocessors suffer from very high temperatures which result to: Increased power/energy consumption More power for cooling Increased leakage power Significant performance loss More often throttling events (frequency/voltage decrease) Lower operating frequencies Increased failure rate Failure mechanisms are exponentially dependent on temperature Increased cost More expensive packaging More expensive cooling solutions

4 Chip Multiprocessors Chip multiprocessors is the current trend in microprocessor design and manufacture Consist out of either identical or different cores Reduce complexity Offer better performance on multiprogramming environments Offer better performance on parallelizable programs Currently available CMPs Pentium D Athlon 64X2 Cell Power 5...

5 The goals Thermal Aware Scheduling (TAS) comes as a solution to all these problems and is applicable on Chip Multiprocessors By improving the thermal characteristics it manages to: Decrease the cost Increase the reliability Increase the performance Decrease the power and energy consumption TAS is a clearly software solution and can be implemented without any hardware modification Development of a proper simulator

6 Outline Temperature problems and TAS TSIC & TAS Related work Thermal Model Thermal Aware Scheduling TSIC: Thermal Scheduling Simulator for CMPs Preliminary Results Work in progress

7 TAS & TSIC TAS manages its benefits by adding temperature awareness to the scheduler of the operating system No simulator is known to exist to evaluate the potential of TAS and quantify its benefits. The main contribution of this work is the development of such a simulator. Our simulator is codenamed: TSIC: Thermal Scheduling SImulator for Chip Multiprocessors

8 TSIC TSIC models the heat flow within the chip to estimate the temperature of each core TSIC is fully parametric Parametric thermal model Simulates CMPs with arbitrary number of cores Simulates workloads of different thermal stress Simulates different core s utilization TSIC handles processes taking into account important real-life events such as: I/O forced context switches Quantum expansion context switches Application variability in the thermal stress caused

9 Outline Temperature problems and TAS TSIC & TAS Related work Thermal Model Thermal Aware Scheduling TSIC: Thermal Scheduling Simulator for CMPs Preliminary Results Work in progress

10 Related Work The most popular microarchitectural temperature simulator is Hotspot from University Of Virginia (LAVA group Prof. Kevin Skadron) Hotspot is publicly available and is widely used by the academic community It has been shown to be sufficiently accurate Models multiple-blocks of the microprocessor Uses an equivalent RC circuit to model the thermal flow within the processor Works with Wattch, a widely used power simulator. Hotspot models only uniprocessors

11 Outline Temperature problems and TAS TSIC & TAS Related work Thermal Model Thermal Aware Scheduling TSIC: Thermal Scheduling Simulator for CMPs Preliminary Results Work in progress

12 Thermal Model The parts of the Chip Multiprocessor that are important for the thermal model

13 Thermal Model The heat spreader For illustration purposes we show it under the chip

14 Thermal Model The multiprocessor

15 Thermal Model The processor cores

16 Thermal Model The temperature of the ambient (the air surrounding the chip) air

17 Thermal Model Local power consumption Τhe main factor that increases the temperature of core

18 Thermal Model Cores can dissipate heat to the ambient through two different directions

19 Thermal Model Vertical heat dissipation to the ambient

20 Thermal Model Lateral heat dissipation to the ambient

21 Thermal Model Internal cores are NOT able to dissipate heat to the ambient laterally

22 Thermal Model Inter-cores heat exchange

23 Thermal Model The temperature equation: T -T T = T + f position,t + f + f local,t ( ) t t t+1 t ( t ) i j t i i 1 i 2 3 i j i di,j ( )

24 Thermal Model The temperature equation: The new temperature of the core (interval t+1) T t+ 1 i T -T = T + f position,t + f + f local,t ( ) t t t ( t) i j i 1 i 2 3 i j i di,j ( t)

25 Thermal Model The temperature equation: The new temperature of the core (interval t+1) The previous temperature of the core (interval t) T -T T = + f position,t + f + f local,t ( j) t t t+1 t ( t ) i j t i Ti 1 i 2 3 j i di, ( ) i

26 Thermal Model The temperature equation: The new temperature of the core (interval t+1) The previous temperature of the core (interval t) T -T T = T + + f + f local,t ( i,j) t t t+ 1 t ( t ) i j t i i f1 position,ti 2 3 i j i d Heat transfer to the ambient, depends on the position of the core and its current temperature ( )

27 Thermal Model The temperature equation: The new temperature of the core (interval t+1) The previous temperature of the core (interval t) t t T ( ) i -Tj T i = T i + f1 position,t i + f2 + f ( ) 3 local j i d i, j (,T ) i t+1 t t t Heat transfer to the ambient, depends on the position of the core and its current temperature Inter-core heat exchange

28 Thermal Model The temperature equation: The new temperature of the core (interval t+1) The previous temperature of the core (interval t) t t T ( ) i -T t+1 t t j T i = T i + f1 position,t i + f 2 + f ( ) 3 loca j i d i, j ( t l,t ) i Heat transfer to the ambient, depends on the position of the core and its current temperature Inter-core heat exchange Heat due to local power consumption

29 Thermal Model The temperature equation: The new temperature of the core (interval t+1) The previous temperature of the core (interval t) T -T T = T + f position,t + f + f local,t ( ) t t t+1 t ( t ) i j t i i 1 i 2 3 i j i di,j ( ) Heat transfer to the ambient, depends on the position of the core and its current temperature Inter-core heat exchange Heat due to local power consumption New temperature is calculated after each thermal interval (Thermal Cycle) More details can be found in the paper

30 Outline Temperature problems and TAS TSIC & TAS Related work Thermal Model Thermal Aware Scheduling TSIC: Thermal Scheduling Simulator for CMPs Preliminary Results Work in progress

31 Thermal Aware Scheduling Future CMPs will embed a large number of cores

32 Thermal Aware Scheduling Future CMPs will embed a large number of cores When a new process is to be executed the Operating System must decide on which core it will be assigned (one of the idle cores will be selected)

33 Thermal Aware Scheduling Future CMPs will embed a large number of cores When a new process is to be executed the Operating System must decide on which core it will be assigned (one of the idle cores will be selected) Thermal Aware Scheduling (TAS) helps define the thermally most appropriate core

34 Thermal Aware Scheduling Future CMPs will embed a large number of cores When a new process is to be executed the Operating System must decide on which core it will be assigned (one of the idle cores will be selected) Thermal Aware Scheduling (TAS) helps define the thermally most appropriate core Different cores on the chip have different cooling abilities

35 Thermal Aware Scheduling Future CMPs will embed a large number of cores When a new process is to be executed the Operating System must decide on which core it will be assigned (one of the idle cores will be selected) Thermal Aware Scheduling (TAS) helps define the thermally most appropriate core Different cores on the chip have different cooling abilities Enhanced Cooling abilities: Good lateral heat dissipation Only two adjacent neighbors

36 Thermal Aware Scheduling Future CMPs will embed a large number of cores When a new process is to be executed the Operating System must decide on which core it will be assigned (one of the idle cores will be selected) Thermal Aware Scheduling (TAS) helps define the thermally most appropriate core Different cores on the chip have different cooling abilities Decreased Cooling abilities: Decreased lateral heat dissipation Four adjacent neighbors of unknown temperature

37 Thermal Aware Scheduling Future CMPs will embed a large number of cores When a new process is to be executed the Operating System must decide on which core it will be assigned (one of the idle cores will be selected) Thermal Aware Scheduling (TAS) helps define the thermally most appropriate core Different cores on the chip have different cooling abilities Different processes have different power consumption characteristics and so cause different thermal stress

38 Thermal Aware Scheduling An example: Execute processes C (cold) and H (Hot) on the CMP shown below The cold process comes first

39 Thermal Aware Scheduling An example: Execute processes C (cold) and H (Hot) on the CMP shown below 2 The best available core is core 1 1

40 Thermal Aware Scheduling An example: Execute processes C (cold) and H (Hot) on the CMP shown below 2 The cold process is assigned to core 1 1

41 Thermal Aware Scheduling An example: Execute processes C (cold) and H (Hot) on the CMP shown below 2 The hot process comes next and is assigned to core 2 1

42 Thermal Aware Scheduling An example: Execute processes C (cold) and H (Hot) on the CMP shown below 2 1 This is inefficient assignment: Although core 2 has reduced cooling abilities it executes a hot process so its temperature is likely to increase soon Core 1 is underutilized as it has enhanced cooling abilities but executes a low demanding workload

43 Thermal unawareness Thermal unawareness can lead to highly unwanted scenarios such as: Hotspot creation High performance loss Non homogeneous temperature among the chip and time Lets see an example...

44 Thermal unawareness High performance loss Execution of a hot process a Although core a is the coolest available core it does not have efficient cooling. Executing the new process on core a will lead to often throttling events and so, significant performance loss. TAS would select core b due to its high cooling efficiency b

45 Outline Temperature problems and TAS TSIC & TAS Related work Thermal Model Thermal Aware Scheduling TSIC: Thermal Scheduling Simulator for CMPs Preliminary Results Work in progress

46 TSIC General C# programming language (Object Oriented) Microsoft Visual Studio.NET 2003 User friendly visual interface Runs on Microsoft Windows operating system The code Detailed code documentation Approximately lines of code Simulation Speed More than 5000 cycles /second for a 36 cores chip Schedulers Very easy to implement a new scheduler

47 TSIC - Full Model To increase accuracy TSIC interleaves a number of thermal cycles between each pair of process cycles Thermal Cycle: Updates the temperature of cores according to the equation presented before: T -T T = T + f position,t + f + f local,t ( ) t t t+1 t ( t ) i j t i i 1 i 2 3 i j i di,j ( ) Process Cycle: Generates and manipulates the workload and assigns processes to cores.

48 TSIC Process Model Active processes exist? Yes Generate processes with random Are Remove there expired any processes running that and have free on a Are characteristics End there of process any idle and cycle cores? assign it to context the Chip execution switch Multiprocessor? cores. (expired processes)? execution cores No Expired processes exist? No Yes Remove expired processes Idle cores exist? No Yes Randomly generate new processes End of process cycle

49 TSIC Thermal Model Thermal model updates the temperature of cores taking into account: Inter-cores heat exchange Local power consumption Vertical heat transfer rate to the ambient Lateral heat transfer rate to the ambient On every thermal cycle it executes an iteration of the equation: T -T T = T + f position,t + f + f local,t ( ) t t t+1 t ( t ) i j t i i 1 i 2 3 i j i di,j ( )

50 TSIC - Operation The main window of the simulator

51 TSIC - Operation Run both models simultaneously

52 TSIC - Parameters Set initial temperatures menu

53 TSIC - Parameters Settings menu

54 TSIC Results Menu

55 TSIC Results Menu

56 TSIC Results Menu

57 TSIC Results Menu

58 Available Schedulers Random scheduler Randomly selects one of the available cores Guarantees equal cores usage Always Coolest Always selects the coolest available core Very easy to implement Neighborhood aware Accounts the temperature of neighboring cores Benefits cores residing at the edge of the chip

59 Outline Temperature problems and TAS TSIC & TAS Related work Thermal Model Thermal Aware Scheduling TSIC: Thermal Scheduling Simulator for CMPs Preliminary Results Work in progress

60 Results The results presented next are just preliminary results and they aim to validate the simulator. More detailed results to proof the efficiency of Thermal Aware Scheduling are in progress. Experimental Setup Different number of cores [36 & 64] Different chip utilizations [50% & 80%]

61 Results Chip-wide Average Temperature 50 Temperature Cores Utilization 50% 36 Cores Utilization 80% 64 Cores Utilization 50% 64 Cores Utilization 80% Random Always coolest Neighborhood aware

62 Outline Temperature problems and TAS TSIC & TAS Related work Thermal Model Thermal Aware Scheduling TSIC: Thermal Scheduling Simulator for CMPs Preliminary Results Work in progress

63 Work in progress Future work for TSIC will focus on the development of more sophisticated schedulers Logging Scheduler Keeps statistics about previous executions of a process to predict its future behavior Allows better scheduling decisions to be made Window Scheduler Takes a window of processes into account while scheduling Allows better scheduling decisions to be made Booster Scheduler Allows frequency increase of a specific core Minimizes the throttling events of a specific core Enhances the performance of a single process Plug-in real application SPEC 95 and SPEC 2000 benchmarks

64 Conclusions TSIC: Thermal Scheduling Simulator for Chip Multiprocessors enables studying: Thermal Aware Scheduling on Chip Multiprocessors. Main characteristics of TSIC: Modular Very fast Fully parametric Multi-simulation modes Visual presentation of all results

65 Questions Thank you! Questions? The CASPER group:

Enhancing Multicore Reliability Through Wear Compensation in Online Assignment and Scheduling. Tam Chantem Electrical & Computer Engineering

Enhancing Multicore Reliability Through Wear Compensation in Online Assignment and Scheduling Tam Chantem Electrical & Computer Engineering High performance Energy efficient Multicore Systems High complexity