An Automotive Case Study ERTSS 2016

Transcription

1 Institut Mines-Telecom Virtual Yet Precise Prototyping: An Automotive Case Study Paris Sorbonne University Daniela Genius, Ludovic Apvrille ERTSS 2016

2 Context Model-oriented Design of Complex Embedded Systems Nowadays current practice in software development for embedded systems Hardware aspects less frequently designed using this kind of approach Models of software components are generally tested/executed on the local host, then integrated on target once available Even if several virtual prototyping platforms are available before the target is available, they require to re-model software elements in a different input format from the one used in models or programming languages 2/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

3 Virtual Prototyping Related Work MARTE [Vidal et al. DATE 2009] AADL [IFIP-WADL 2004, Ben Youssef et al. ETSS 2014] Arcadia/Capella [Polarsys 2008, [ERTSS 2012] Aims at fully integrated way to model critical software components and candidate hardware architectures Joint use of both AVATAR and SocLib was not well integrated: description of the hardware execution environment only in textual form outside of SysML models 3/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

4 Overview of the Contribution: Method 1. Model refinement 2. Selection of OS, setting of options (scheduling algorithm,... ) 3. Selection of a hardware platform and of task allocation scheme 4. Code generation (press-button approach) 5. Manual code improvement 6. Code compilation and linkage with OS 7. Simulation platform boots the OS and executes the code 8. Execution analysis: sequence diagram or debugger (e.g. gdb) 4/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

5 Overview of the Contribution: Tooling 5/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

6 AVATAR Model-oriented solution for the analysis and design of embedded software SysML diagrams describe the software aspects of the system, its safety and security properties Fully supported by the free software TTool Edit AVATAR models Simulation Formal verification Like in most UML approaches, simulation and formal verification rely on a purely timed functional model, without considering any hardware target (CPU, bus, etc.) 6/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

7 SoCLib and MutekH Hardware platform simulator: SoCLib Virtual prototyping of complex Systems-on-Chip Supports several models of processors, buses, memories Example of CPUs: MIPS, ARM, SPARC, Nios2, PowerPC Two sets of simulation models: TLM = Transaction Level Modeling CABA = Cycle Accurate Bit Accurate Embedded Operating System: MutekH Natively handles heterogeneous multiprocessor platforms POSIX thread support Note: any Operating System supporting POSIX threading that can be compiled for SoCLib could be used 7/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

8 Case Study: An Automotive Application Automotive embedded system Made upon a hundred of Electronic Control Units (ECUs) Interconnection with CAN / FlexRay / MOST Automatic Braking Application Taken from Intelligent Transport System applications and from the EVITA european project 1. Obstacle is detected by a car 2. Information is broadcasted to neighborhood cars 3. A car receiving such an information may decide to make an automatic emergency braking w.r.t.: Vehicle dynamics, vehicle position,... Plausibility check 8/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

9 Active Braking Use Case 9/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

10 Deployment Diagram SysML representation of hardware components, their interconnection, tasks and channels Platforms can be modified in a matter of minutes A valid platform must contain at least one CPU, one memory bank and one terminal for observing the progress By choice, and to be discussed, some details (interrupt controller, simulation aides) are currently transparent to the user 10/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

11 Deployment Diagrams AVATAR specification Deployment Diagram 11/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

12 Deployment Diagram for the Case Study 12/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

13 New Tool Chain Generate fully executable SoCLib specification for MPSoC from Deployment Diagram and software component diagrams block0.c Block Diagram and State Machine SyntaxChecker AVATARSpecification... AVATAR2SOCLIB blockn.c main.c libavatar AVATARDDSpecification LdscriptGenerator ldscript Deployment Diagram DDSyntaxChecker deployinfo.h TopcellGenerator top.cc crosscompiler Application Binary loader SoCLib-cc SoCLib Executable 13/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

14 Model Transformation 1. Libavatar Runtime for SoCLib, implements the AVATAR operators 2. DDSyntaxChecker checks the syntax of the deployment diagrams and identifies their elements 3. AVATAR2SOCLIB translates AVATAR blocks (i.e., software components) into C POSIX tasks and generates the main program 4. TopcellGenerator generates a SystemC top cell for cycle accurate bit accurate simulation 5. LdscriptGenerator generates the linker script, taking into account the mapping specified in the deployment diagram 14/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

15 The AVATAR Runtime Library of functions which capture the semantics of the AVATAR operators that appear in the code of the tasks (delay, asyncread, etc.) and implements them using C/POSIX primitives Focuses on channels; interconnect latencies and cache effects make them difficult to implement efficiently on a MPSoC platform SoClib provides an efficient implementation of asynchronous channels as sowtware objects stored in on-chip memory, based on the Kahn model In order to run on a SoCLib platform, instead of the local workstation, the runtime had to be adapted 15/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

16 Prototyping: Top Cell Generation SystemC instanciation of components, netlist, table associating memory segments, charging of code Some components are transparent to the user (interrupts, simulation infrastructure) 16/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

17 Linker Script Generation Handling the mapping of channels is rather difficult since it is related to the main program, the top cell and the linker script (ldscript) File which defines the memory layout; Associates each entry section to an output section, which receives its address in memory Mapping information from Deployment Diagram is used to generate a file to be included by the ldscript generator d a t a l d r. l o a d f i l e ( s t d : : s t r i n g ( k e r n e l p ) + ";. data ;. channel0 ;.... channel14 ;. cpudata ;. contextdata " ) ; 17/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

18 Code Generation Difficulties Implementing AVATAR channels with existing paradigm for SoCLib (software channel mapped to shared memory) Co-existence of synchronous and asynchronous channels Central request management required for synchronous channels 18/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

19 Extract from generated code for the DrivingPowerReductionStrategy block (1) #i n c l u d e " DrivingPowerReductionStrategy.h" s t a t i c u i n t 3 2 t getreducepowerorder ;... v o i d mainfunc DrivingPowerReductionStrategy ( t r u c t mwmr s channels DrivingPowerReduc t i o n S t r a t e g y [ ] ) { st r uc t mwmr s DangerAvoidanceStrategy reducepower DrivingPowerReductionStrategy get ReducePowerOrder= channels DrivingPowerReductionStrategy [ 0 ] ; i n t v a l u e = 0 ; i n t minreducepowertime = 1 0 ; i n t maxreducepowertime = 2 0 ; i n t c u r r e n t S t a t e = STATE START STATE ;... p t h r e a d c o n d i n i t (& mycond, NULL ) ; f i l l L i s t O f R e q u e s t s (& l i s t, myname, & mycond, & mainmutex ) ; 19/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

20 Extract from generated code for the DrivingPowerReductionStrategy block (2) w h i l e ( c u r r e n t S t a t e!= STATE STOP STATE ) { s w i t c h ( c u r r e n t S t a t e ) { case STATE START STATE : c u r r e n t S t a t e = STATE WaitForReducePowerOrder ; break ; case STATE WaitForReducePowerOrder : p a r a m s 0 [ 0 ] = &v a l u e ; makenewrequest(& r e q 0, 853, RECEIVE SYNC REQUEST, 0, 0, 0, 1, p a r a m s 0 ) ; req0. syncchannel = & DangerAvoidanceStrategy reducepower\ DrivingPowerReductionStrategy getreducepowerorder ; returnrequest = executeonerequest (& l i s t, & req0 ) ; c l e a r L i s t O f R e q u e s t s (& l i s t ) ; D r i v i n g P o w e r R e d u c t i o n S t r a t e g y a p p l y R e d u c e P o w e r ( v a l u e ) ; c u r r e n t S t a t e = STATE WaitForReducePowerToBePerformed ; break ; case STATE WaitForReducePowerToBePerformed : waitfor ( minreducepowertime, maxreducepowertime ) ; DrivingPowerReductionStrategy reducepowerdone ( ) ; c u r r e n t S t a t e = STATE WaitForReducePowerOrder ; break ; } } r e t u r n NULL ; } 20/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

21 Code Generation: Declaration of Channels s y n c c h a n n e l D a n g e r A v o i d a n c e S t r a t e g y r e d u c e P o w e r DrivingPowerReductionStrategy getreducepowerorder ; u i n t 3 2 t c o n s t DangerAvoidanceStrategy reducepower D r i v i n g P o w e r R e d u c t i o n S t r a t e g y g e t R e d u c e P o w e r O r d e r l o c k= LOCKSADDR+0x0 ; s tr uc t mwmr status s D a n g e r A v o i d a n c e S t r a t e g y r e d u c e P o w e r D r i v i n g P o w e r R e d u c t i o n S t r a t e g y g e t R e d u c e P o w e r O r d e r s t a t u s = MWMR STATUS INITIALIZER (1, 1 ) ; u i n t 8 t DangerAvoidanceStrategy reducepower DrivingPowerReductionStrategy getreducepowerorder data [ ] ; s tr uc t mwmr s DangerAvoidanceStrategy reducepower D r i v i n g P o w e r R e d u c t i o n S t r a t e g y g e t R e d u c e P o w e r O r d e r = MWMR INITIALIZER ( 1, 1, D a n g e r A v o i d a n c e S t r a t e g y r e d u c e P o w e r D r i v i n g P o w e r R e d u c t i o n S t r a t e g y getreducepowerorder data,& DangerAvoidanceStrategy reducepower DrivingPowerReductionStrategy getreducepowerorder status, " DangerAvoidanceStrategy_reducePower DrivingPowerReductionStrategy_getReducePowerOrder ", D a n g e r A v o i d a n c e S t r a t e g y r e d u c e P o w e r D r i v i n g P o w e r R e d u c t i o n S t r a t e g y getreducepowerorder lock ) ; 21/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

22 Code Generation: Extract from Main Program i n t main ( i n t argc, char a r g v [ ] ) {... s tr uc t mwmr s channels array DrivingPowerReductionStrategy [ 1 ] ; channels array DrivingPowerReductionStrategy [ 0 ] =&D a n g e r A v o i d a n c e S t r a t e g y r e d u c e P o w e r D r i v i n g P o w e r R e d u c t i o n S t r a t e g y getreducepowerorder ; p t r =m a l l o c ( s i z e o f ( p t h r e a d t ) ) ; t h r e a d D r i v i n g P o w e r R e d u c t i o n S t r a t e g y= ( p t h r e a d t ) p t r ; a t t r t = m a l l o c ( s i z e o f ( p t h r e a d a t t r t ) ) ; a t t r t >cpucount = 2 ; debugmsg ( " Starting tasks " ) ; pthread create (& thread DrivingPowerReductionStrategy, NULL, mainfunc DrivingPowerReductionStrategy, ( v o i d ) channels array DrivingPowerReductionStrategy ) ; 22/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

23 Using TTool/SoCLib 23/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

24 Using TTool/SoCLib 24/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

25 Limitations Currently Overcome Variations of the interconnect (bus, CAN, etc.) Central manager handling synchronous and asynchronous channels Mid and longer term Simulation speed Currently PowerPCs only: crosscompilers Clustered interconnect 25/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping

26 Future Work Extensions Integration of application specific co-processors Animation and performance evaluation with Lip6 tools Feedback of results for Design Space Exploration Long term : Design Space Exploration METROPOLIS SPADE SESAME ARTEMIS To try/download TTool: 26/26 Jan.29, 2016 Institut Mines-Telecom, Paris Sorbonne Universites Virtual Yet Precise Prototyping