Digital Systems. Validation, verification. R. Pacalet January 4, 2018
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1 Digital Systems Validation, verification R. Pacalet January 4, /98
2 Simulation Extra design tasks Reference model Simulation environment A simulation cannot be exhaustive Can discover a bug Cannot guarantee correctness Simulation before and after synthesis sometimes behave differently Usually CPU intensive 6/98 R. Pacalet January 4, /98
3 Simulation Simulation-based verification Generate input stimulus Random Driven by a given functionality Generated from constraints (Vera, Verisity) Generate expected results (reference model) Simulate with input stimulus Compare simulation output with expected results (offline or online) 12/98 R. Pacalet January 4, /98
4 Formal verification, history The theory dates back to the 70 s In 1980 systems with about 10 6 states could already be verified In 1990 Clarke et al. (CMU) dramatically improve model checking algorithms with SMV states Hard critical bugs discovered in real world designs Cache coherency protocol,... Today Commercial tools exist Industry is interested Very large states space systems verified 16/98 R. Pacalet January 4, /98
5 Combinational equivalence checking Comparison of 2 designs Synthesizable or synthesized (Almost) same memory elements (re-targeting) Fast (several runs/day, multi-million gates designs) Exhaustive Affordable (tools, learning curve) Reference golden model needed 21/98 R. Pacalet January 4, /98
6 Combinational equivalence checking The size of a BDD highly depends on the variable ordering Function: a1b1 +a2b2 +a3b3 a1 a1 b1 a2 a2 a2 a3 a3 a3 a3 b2 b1 b1 b1 b1 a3 b2 b2 b3 b a1 < b1 < a2 < b2 < a3 < b3 a1 < a2 < a3 < b1 < b2 < b3 25/98 R. Pacalet January 4, /98
7 Sequential equivalence checking Comparison of 2 designs Synthesizable or synthesized Without constraints on memory elements Slow and memory-hungry (limited to a few hundreds of DFF) Exhaustive Affordable (tools and learning curve) Reference golden model is needed 30/98 R. Pacalet January 4, /98
8 Model checking Purely functional (physical characteristics ignored) A design passes property iff No counter-example Used to validate Functionality of synthesizable model Modifications 35/98 R. Pacalet January 4, /98
9 The controller sel IDLE pss=0 ack=0 sel req READY pss=0 ack=0 sel ( req) sel sel req PASS pss=1 ack=0 sel ( req) req BUSY pss=0 ack=1 req 39/98 R. Pacalet January 4, /98
10 Temporal logics Classical boolean logic true,false,,,,, Atomic formula p = ((ack = 1) (req = 0)) Temporal operators characterize execution (path in state tree) X (next): Xp = next state satisfies p (STATE = PASS) X(STATE = IDLE) F (Futur): Fp = a future state satisfies p (req = 1) F (ack = 1) 43/98 R. Pacalet January 4, /98
11 Temporal logics Path - time pairs AGp: p always satisfied, for every execution, for every state (safety) AG ((acka = 1) (ackb = 1)) EGp: there exist one execution for which p always satisfied EG (reqa = 1) AXp: starting from current state all next states satisfy p EXp: starting from current state there exist one next state satisfying p 47/98 R. Pacalet January 4, /98
12 Temporal logics CTL: CTL* with the constraint that every temporal operator (X,F,G,U) is preceded by a path operator (A,E) CTL formulas are state formulas CTL formulas depend only on the current state, not on the current execution (path) CTL cannot write F FCTL: extension of CTL (F for Fair) allowing to express F The model checking on CTL or FCTL is more efficient than on LTL But designers prefer LTL 51/98 R. Pacalet January 4, /98
13 Counter-examples Counter-example may be finite... Safety AG(r) : r,g... Or infinite Liveness AF (g) : r,r,r,r,... Infinite counter-example made of stem and cycle Cycle Stem 55/98 R. Pacalet January 4, /98
14 Why using non-determinism? To model environments Example System to verify = arbiter + controller Environment of system = clients Requests asserted in non-deterministic way Non-determinism allows modeling of any behavior of clients In the following $ND will be our non-deterministic statement 1 wire rand ; 2 assign rand = $ND(0,1) ; 3 i f ( rand )... 1 s i g n a l rand : boolean ; 2 rand <= $ND( false, t r u e ) ; 3 i f ( rand ) then /98 R. Pacalet January 4, /98
15 Algorithms of CTL model checking Notations Let Q be the set of states of A Let L(q) be the set of atomic properties p satisfied in state q Let T be the set of transitions (q,q ) from state q of A to another state q of A Let degree(q) be the number of successors of q in state diagram of A Complexity of model checking of CTL formula ϕ is O( A ϕ ) 63/98 R. Pacalet January 4, /98
16 Algorithms of CTL model checking Case #4: ϕ = EX ψ procedure MARKING(ϕ) O( Q + T ) MARKING(ψ); for every q Q do q.ϕ false; Initialization for every (q,q ) T do if q.ψ then q.ϕ true; end if end for end for end procedure 67/98 R. Pacalet January 4, /98
17 Specification of whole system? Exercise #6: If client requests the bus, it will not release its request until it is granted the bus? Exercise #7: If client A holds the bus and client B requests it, it is impossible that A releases the bus, then requests and is granted the bus again before client B is granted the bus 71/98 R. Pacalet January 4, /98
18 Functional simulation Warning: simulation speed and debugging capabilities frequently antinomic Dynamic verifications (VHDL) Warning: simulation speed and expressiveness frequently antinomic Parallelism Sequential scheduling Variables versus signals 77/98 R. Pacalet January 4, /98
19 Gate level simulation Netlist (network of interconnected gates) can also be simulated Gate level simulation with or without timing information (back-annotation, VITAL/SDF) Different temporal models, with different accuracy vs. performance ratios Prop Ramp Delay Input Slope Model Wave tabular... 82/98 R. Pacalet January 4, /98
20 Electrical simulation Transistor-based electrical simulation (SPICE, ELDO) provides more accurate results Used for standard cells characterization or simulation of full custom designs Very slow, very accurate Unavoidable in some specific cases Limited to few hundreds of transistors 87/98 R. Pacalet January 4, /98
21 What is it used for? Speed up simulation of synthesizable code Warning: not always best choice Warning: what you simulate not always what you think Speed up fault simulation Emulate chip in system environment Ease hardware-software co-design Increase designer s confidence Heat building 92/98 R. Pacalet January 4, /98
22 Verification effort Figure : Breakdown of verification effort (ITRS 1999) 97/98 R. Pacalet January 4, /98
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