New Exploration Frameworks for Temperature-Aware Design of MPSoCs. Prof. David Atienza

Transcription

1 New Exploration Frameworks for Temperature-Aware Degn of MPSoCs Prof. David Atienza Dept Computer Architecture and Systems Engineering (DACYA) Complutense Univerty of Madrid, Spain Integrated Systems Lab (LSI) École Polytechnique Fédérale de Lausanne (EPFL), Switzerland Château St. Gerlach, Valkenburg, The Netherlands Evolution of Electronics to Multi-Processor System-on on-chip (MPSoC) Roadmap continues: nm CMOS 90nmCMOS 65nm CMOS 45nm Multi-Processor System-on on-chip (MPSoC) architectures: complex HW and SW PE CPU [Cell Local Multi-Processor PS3] i/o hierarchy Multi-Processor Operating 80-tile System (MPOS) I/0 PE 1.28TFLOPS PE PE MPSoC INTEL I/0 SRAM [ISSCC SRAM 07] PE Sw application I/O 1... SRAM I/O P E R I P H E R A L S Sw application N SDRAM main memory 2

2 Degn Issues in MPSoCs MPSoCs have very sophisticated architectures Complex components and CAD tools very expenve Time-closure issues, system speed decreased Increang thermal issues Hot-spots, non-uniform thermal gradients [Sun, 1.8 GHz Sparc v9 Microproc] [Santirini, EDN, March 05] [Sun, Niagara Broadband Processor] [Coskun et al 07, Sun] High chances of thermal wear-outs and very short lifetimes! 3 Advocating Thermal-Aware Degn Integration of HW/SW modeling and management Thermal and architectural information HW-SW emulation frameworks HW Thermal monitoring HW Tuning knobs HW reconfigurable architecture HW-Based Thermal Management Policies SW-Based Thermal Management Policies HW and compiler-level level algorithms OS and application-level level algorithms 4

3 Introduction Outline MPSoC thermal modeling Computational infrastructure Closed-loop loop statistics extraction system Thermal model Case studies Summary and concluons 5 MPSoC Thermal Modeling Problem Continuous heat flow analys Capture geometrical characteristics of MPSoCs Explore different packaging features and heat nk characteristics Time-variant heat sources Transtor switching depends on MPSoC run-time activity Dynamic interaction with heat flow Very complex computational problem! 6

4 MPSoC Thermal Modeling State-of of-the-art MPSoC Modeling and Exploration: 1. SW mulation: Transactions, cyclec ycle-accurate (~100 KHz) [Synopsys Realview, Mentor Primecell, Madsen et al., Angiolini et al.] At the dered cycle-accurate level, they are too slow for thermal analys of real-life life applications! 2. HW prototyping on FPGAs: Core dependent (~MHz): [Cadence Palladium II, ARM Integrator IP, Heron Eng, Marescaux et al.] Very expenve and late in degn flow, large man- power to perform MPSoC system-level exploration! Combination of cycle-accurate MPSoC behavior and run-time IC heat flow modeling is unheard of Heat Flow Modeling: 1. Software thermal/power models [Skadron et al., Kang et al.] Too computationally intenve, not able to use detailed run-time inputs from MPSoC components! 7 Orthogonalizing MPSoC Thermal Modeling and Analys Multi-Processor Operating System I/O (MPOS) CPU CPU Sw app 1... Sw app N SRAM SRAM SRAM I/O sniffer CPU sniffer CPU sniffer sniffer sniffer sniffer FPGA sniffer sniffer sniffer interconnect interconnect Energy Temperature (T) SW thermal estimation tool (Host PC) Framework: MPSoC behavioral model on reconfigurable HW interacting with efficient thermal estimation 8

5 Emulation vs. Simulation/Prototyping To emulate an electronic system is to build a platform capable of imitating its behaviour in an accurate and analyzable way SW Simulation Lower performance Maximum flexibility Poor accuracy in thermal analyses HW Emulation Good performance Good flexibility Independent from actual HW Accurate thermal modelling HW Prototyping Close to final performance Reduced flexibility Dependent on available HW (May alter results) More efficient than SW mulation More flexible than pure HW prototyping Thermal behavior analys earlier than HW prototyping 9 MPSoC Architecture Emulation Proc. Controller shared memory link D-Cache I-Cache Scratchpad Cacheable Private Emulated MPSoC Sub-system 1 Emulated MPSoC Sub-system N Procesng cores (hard & soft) Interconnections (buses & NoCs) Comm. Bridge Interchangeable Interconnect (System Buses and NoCs) Main. Mem Sub-system Comm. Bridge Shared Main 1 Interrupt controller HW semaphore subsystem (cache, main, ) Extra peripherals (HW semaphore, interrupt controller) 10

6 Degning the Emulated Architecture What we want VS. What we have Dered: A fast memory Latency: 1 cycle Mapping Phycal resource: On board BRAM Latency: 1 cycle Proc. LOCAL BUS Controller Cache Cache (BRAM) Main 11 Degning the Emulated Architecture What we want VS. What we have Dered: Big memory Latency: 3 cycles Mapping Phycal resource: On board DDR RAM Latency: 5 cycles Proc. LOCAL BUS Controller Cache Main 12

7 Degning the Emulated Architecture 2) Clock management VPCM Module (Frequency Scaling Module) Virtual CLK Virtual CLK suppreson Proposed solution: Mapping + Clock management Proc. LOCAL BUS Controller Cache Main Main (DDR RAM) 1) Mapping 13 Statistics Extraction Subsystem Another clock domain (100 MHz) Dedicated bus & HW: Not intruve, concurrently running 2 Types of statistics: Event counting accesses tracing 14

8 Sending Energy Values Emulated MPSoC Event Event Event SNF_0 Log Look-Up table SNF_1 Log Look-Up table SNF_N Log Look-Up table Statistics Bus Messag 0 Messag 1 Messag n VPCM Statistics Manager (procesng) BRAM buffer Packet 2 Packet 0 Packet 1 When connection available Ethernet Controller Sw thermal estimation tool 15 Receiving Temperatures Sensor_0 Emulated MPSoC Sensor_1 Sensor_N Statistics Bus Messag 0 Messag 1 Messag n VPCM Statistics Manager (procesng) BRAM buffer Packet 0 Ethernet Controller Sw thermal estimation tool 16

9 Chip and Package Heat Flow Modeling Model interface Input: power model of MPSoC components, geometrical properties Output: temperature of MPSoC components at run-time Thermal circuit: 1 st order RC circuit Heat flow ~ Electrical current ; Temperature ~ Voltage Heat spreader and IC composed of elementary blocks Cu cu cu cu cu Si thermal conductivity depends on temperature (IMEC & Freescale, 90nm) IC package Heat spreader Package pin IC die PCB Thermal capacitance conductance matrix matrix C,1 G 1,2 -G 1,2. C,2 -G 2,1 G 2,1 C t k = - G (t k )t k + p k ; k = 1..m Temperature change C cu,n Temperature power consumption vector at instant vector k 17 SW Thermal Estimation Tool for MPSoCs Creating linear approximation while retaining variable Si thermal conductivity: Si thermal conductivity linearly approx. : G (t k ) = I + q Si thermal conductivity linearly approx. : G i,j Numerically integrating. in discrete time domain the t k : t k+1 = A(t k )t k + Bp k ; k = 1..m 1600 A(t k ) = (I - d t C G(t k )) ; B = d t C Non-linear -1 thermal estim. Heat flow estimation Time (S.) Complexity scales linearly with the number of modeled cells (mulated on Time P4@ 3GHz) step chosen small 800 thermal library enough validated for convergence against 3D finite element 200 model (IMEC & Freescale) 0. C t k = - G (t k )t k + p k ; k = 1..m i,j (t = I + q t k Si thermal conductivity dependent on temperature Proposed linear thermal estimation

10 Introduction Outline MPSoC thermal modeling Computational infrastructure Closed-loop loop statistics extraction system Thermal model Case studies Summary and concluons 19 Case Study 1: 4-Core 4 MPSoC MPSoC Philips board degn: 4 processors, DVFS: 100/500 MHz Plastic packaging Software: Image watermarking, video rendering Power values for 90nm: Element Max Power (mw) 100 MHz Max Power (mw) 500 MHz Processor 2,92 x ,02 x 10 3 D-Cache 1,42 x ,10 x 10 2 I-Cache 1,42 x ,10 x 10 2 Priv Mem 0,61 x ,75 x 10 2 AMBA 0,31 x ,68 x

11 Thermal Validation 4-Core 4 MPSoC MPARM: MPSoC SW mulator: power/thermal models tuned for Philips Simulations too slow: 2 days for 0.18 real sec (12 cells) HW thermal emulation able to validate policies at run-time Very fast validation of MPSoC Dynamic Voltage and Frequency Scaling (DVFS) ) based on thresholds weeks of mulation?! run-time thermal behavior and management HW/SW Thermal Emulation time 45 sec (128 cells)! DVFS ON: 500/100 MHz. Package limit (~85ºC) 500 MHz. 100 MHz. 21 Case Study 2: Multi-Core Thermal Control HW: Sun 8-core 8 Niagara MPOS: Solaris Multi-Core SW: Web & gnal procesng Standard threshold-based DVFS Total run-time of benchmarks: 180 sec 106 sec (45% performance improvement) Proposed Convex-Based DVFS Enhancing thermal control in 90nm multi-cores 22

12 Introduction Outline MPSoC thermal modeling Computational infrastructure Closed-loop loop statistics extraction system Thermal model Case studies Summary and concluons 23 Concluons Shrinking is providing new procesng capabilities through MPSoCs, but creating critical thermal issues Need for new thermal-aware aware modeling methods Orthogonalization of behavior extraction and thermal modeling Novel MPSoC emulation on reconfigurable HW and SW thermal modeling to efficiently extract the behavior of time-variant heat sources Closed-loop loop thermal evaluation framework enabling run-time testing of thermal management in real MPSoC platforms Validation with commercial MPSoC platforms: Fast exploration of thermal behavior of complex MPSoCs Effective tuning of thermal management Thermal run-away avoided with HW-based policies, max. throughput Thermal balancing with negligible performance overhead 24

13 QUESTIONS? Acknowledgements: UCSD / Sun IMEC / Philips Freescale semiconductors 25