NPSAT1 Solar Cell Measurement System
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1 NPSAT1 Solar Cell Measurement System Presented by Captain John Salmon, USMC Space Systems Academic Group 777 Dyer Rd., Bldg. 233 Code (SP/Sd), Rm. 125 Monterey, CA (831)
2 Topics NPSAT1 Overview and Operations Solar Cell Measurement System Overview Solar Cells Cell Measurement Circuit Simulation and Results Test Circuit and Results Design Changes and Error Budget Digital Electronics Summary and Questions Solar Cell Measurement System NPSAT1 2
3 NPSAT1 Overview Class D spacecraft High Risk Minimal cost effort Contains 7 Experiments Nadir pointing, 3-axis stabilized Mission (STP-1) Parameters 560 km ± 10 km alt., circular 35.4 inclination Earliest launch: March 2006 Solar Cell Measurement System NPSAT1 3
4 Sun Sensors Mid-Panels Experimental Solar Cells Thermistors SMS Electronics NPSAT1 Configuration Commercial Triple Junction Cells
5 SMS Operations NPSAT1 powered on as it enters sun soak and before entering eclipse SMS health and calibration is checked Sun sensor readings used to calculate which cell normal vectors are within a 60º sun angle cone Temperature sensors monitored until temperatures stabilize Solar Cell Measurement System NPSAT1 5
6 SMS Operations Experiment ops can be tuned by updating program parameters Solar Cell Measurement System Control Program updateable by uploading RAM picture via the Command and Data Handler Ability to vary sweep parameters Number of sample points Maximum sun angle Number of sweeps (solar cell temperature gradient) Solar Cell Measurement System NPSAT1 6
![Triple Junction Solar Cells 100 80 GaInP GaAs Ge Total AM0 Efficiency [%] 60 40 20 0 0.](/docs-images/80/80881949/images/7-1.jpg "3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.")
7 Triple Junction Solar Cells GaInP GaAs Ge Total AM0 Efficiency [%] Wavelength [µm] Solar Cell Measurement System NPSAT1 7
8 Triple Junction Solar Cells P MAX I SC V OC Solar Cell Measurement System NPSAT1 8
9 SMS Block Diagram
10 Mid-Panel Layout Thermistor Under aluminum substrate Between cells SMS Experiment Cells 22 Experimental Triple Junction 2 Commercial Dual Junction Experimental Triple Junction Cell Strings Solar Cell Measurement System NPSAT1 10
11 Silicon Cell Simulation Circuit 1.01M -5Vdc 12Vdc -12Vdc.432Adc Solar Cell Protection Diode k V- 1 OUT OP-421/AD V+ 12Vdc Vout Vin Vdc 2-11 OP-421/AD V+ 1 OUT V- -12Vdc 2N M R k 6.7 Solar Cell Measurement System NPSAT1 11
12 Simulation Results Current(mA) AD620 Simulation Diff. Amp Simulation Volts Simulation results of both development circuits Differential Amplifier with 1% Resistor tolerance Ideal / Instrumentation Amplifier measurement Solar Cell Measurement System NPSAT1 12
13 Development Board Test Results Current(mA) Labview Solar Cell Protection Diode Mux Output Load Point Volts Solar Cell Measurement System NPSAT1 13
14 Silicon Cell Simulation Circuit 1.01M -5Vdc 12Vdc -12Vdc.432Adc Solar Cell Protection Diode k V- 1 OUT OP-421/AD V+ 12Vdc Vout Vin Vdc 2-11 OP-421/AD V+ 1 OUT V- -12Vdc 2N M R k 6.7 Solar Cell Measurement System NPSAT1 14
15 Design Changes Eliminate resistor variation floating voltage input to differential amplifier Use of instrumentation amplifier Better control on current sink High precision / Low temperature drift resistor High common mode Operational Amplifier Solar Cell Measurement System NPSAT1 15
16 Error Budget Error Source Development 1 Circuit Calculation Development 1 Total Error (ppm) Development 2 Circuit Calculation Development 2 Total Error (ppm) Digital-to-Analog Converter FPGA PWM-Based FPGA PWM-Based Operational Amplifier OP421FY OP497F Current Gain Resistor.1% Tolerant Resistor % Tolerant Resistor Total Current Error Total Current Error Voltage Sensor OP-421FY Differential Amp with 0.1% Resistors AD620 Instrumentation Amp Comparator Input to ADC AD AD Analog-to-Digital Converter FPGA Based Σ FPGA Based Σ Total Voltage Error Total Voltage Error Grand Total Error or 1.54% Grand Total Error or 0.295% Solar Cell Measurement System NPSAT1 16
17 Future Tests Solar Panel Sine Plate Test IV Curves at angle Test Sun Angle Sensors LabView with I/O card Test Multiplex Capability Develop Controller algorithm Solar Cell Measurement System NPSAT1 17
18 Digital Electronics UTMC 80C196KD RadHard 16-bit, 20 MHz µcontroller based on Intel 196 Communication with C&DH via on-board UART Common Digital Architecture for SMS, EPS, and ACS Xilinx XCVR300 FPGA Allows implementation of data converters Step towards System-on-a-Chip Design Flexibility Ability to change on orbit Solar Cell Measurement System NPSAT1 18
19 FGPA SEU Mitigation TMR Route signal through three separate paths Signals majority voted at each feedback All power, ground and clock signals for circuit are tripled Signal minority voted at output pins with tri-state buffers Solar Cell Measurement System NPSAT1 19
20 FGPA SEU Mitigation Reconfiguration Scrub Partial Reconfiguration Solar Cell Measurement System NPSAT1 20
21 Summary Circuit to provide IV-Curves of 22 Experimental Triple Junction Cells and 2 Dual Junction Control Cells Additional parameters provided to normalize curves Timestamp Temperature Sun Angle Ability to multiplex through variable number of cells with minimal error and addition of hardware Solar Cell Measurement System NPSAT1 21
22 Questions? Solar Cell Measurement System NPSAT1 22
23 Backup Slides Solar Cell Measurement System NPSAT1 23
24 NPSAT1 Experiments Supports current DoD needs and research Lithium ion battery technology Experimental triple-junction solar cells Experiments Solar cell measurement system (SMS) Configurable Fault Tolerant Processor (CFTP) COTS micro-electromechanical systems (MEMS) rate sensor COTS visible imager (digital camera) Solar Cell Measurement System NPSAT1 24
25 NPSAT1 Experiments Experiments (cont.) Coherent electromagnetic radio tomography (CERTO) beacon Langmuir Probe Solar Cell Measurement System NPSAT1 25
26 Face 5 ITJ Cells 8,9 Exp String 4 Temp 4 Face 6 NPSAT1 Top View ITJ Cells 10 Exp String 5 Reference Cell 0 Temp 5 Face 7 ITJ Cells 11,12 Exp String 6 Temp 6 Face 8 ITJ Cells 13,14 Exp String 7 Temp 7 Notes: 1. All short Panels except those on faces 6 and 12 have 1 string of experimental ITJ cells and an additional 2 ITJ cells which are not connected to any array. 2. The Short panels on faces 6 and 12 have 1 string of experimental ITJ cells and an additional 2 cells, one of which is an experimental ITJ cell and the other a dual junction standard cell. The additional 2 cells are not connected to any array. 3. Each Short panel has one temperature Sensor Sun Sensor 1 Face 4 ITJ Cells 6,7 Exp String 3 Temp 3 Face 9 ITJ Cells 15,16 Exp String 8 Temp 8 Sun Sensor 2 3 X Face 3 ITJ Cells 4,5 Exp String 2 Temp 2 Face 10 ITJ Cells 17,18 Exp String 9 Temp 9 Face 2 ITJ Cells 2,3 Exp String 1 Temp Face 1 ITJ Cells 0,1 Exp String 0 Temp 0 Face 12 ITJ Cells 21 Exp String 11 Reference Cell 1 Temp 11 Face 11 ITJ Cells 19,20 Exp String 10 Temp 10 Sun Sensor 3 Y Z (Nadir) Velocity Vector X
27 SMS Block Diagram
28 Analog Board Electronics Current sink circuits Analog multiplexing Current sink circuits for 22 TJ and 2 standard cells 6 Goodrich Sun sensor signal conditioning circuits 360º in azimuth, 128º in elevation 3 pair placed 120º apart on NPSAT1 s top panel Thermistor signal conditioning circuit (Omega 44008) 12 Thermistors placed one on each satellite face between cell pairs Calibrated voltage sources Solar Cell Measurement System NPSAT1 28
29 Temperature Sensors Omega Thermistor 0.2ºC accuracy Voltage read across thermistor with current source Temperature Adjustment to IV-curve Solar Cell Measurement System NPSAT1 29
30 Sun Angle Sensors Goodrich DT Module Sun Sensor Three-pair set on top of cylinder +/- 64º Elevation 360º Azimuth ma ma ma ma 1 A B L α = tan A+ B H 0.00 ma ma ma A B y Degrees ma ma Solar Cell Measurement System NPSAT1 30
31 Data Converters Pulse Width Modulator based 12-bit DAC Solar Cell Circuit input to Analog MUX Delta-Sigma 12-bit ADC Built-in PWM DAC for feedback Solar Cell Circuit and Temperature Senors output from Analog MUX Sun Angle Sensors each have dedicated ADC for simultaneous read Solar Cell Measurement System NPSAT1 31
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