Lecture 10, ATIK. Data converters 3

Transcription

1 Lecture, ATIK Data converters 3

2 What did we do last time? A quick glance at sigma-delta modulators Understanding how the noise is shaped to higher frequencies DACs A case study of the current-steering DAC architecture. Suggesting some common implementation and architectural details Impact of impedance Impact of mismatch Some extras needed 289 of 561

3 What will we do today? Case-study pipelined ADC Architecture and a general overview Error correction techniques Sample-and-hold design Comparator design Wrap-up 290 of 561

4 First - the subranging ADC - Basic operation The converter "zooms" a range and converts the residue. If flash is used as subconverter, there is only 2 n 2m comparators vi n t 2 vi n n T n S/H n T n-bit ADC n-bit DAC D N,, m 1 m-bit ADC D m,, 1 w i n nt N =n m n n T =2 vi n nt w i n n T Another analog adder is required as well as a gain circuit, which limits the speed. 291 of 561

5 Pipelined ADC in one picture Multiple subranging ADC in series v ref vi n A series of refinements, zoomins, of the convertible range 1 0 Assume same range in each stage vi n t 1 nt 3 n T 2 nt 4 nt 292 of 561

6 Pipelined ADC - delays Balance the delays and "cleverly" distribute the clock to avoid race v i n t T T T T T T T T T T Clock direction to avoid race A pipelined ADC will have longer latency 293 of 561

7 Pipelined ADC - sensitive towards errors Any misinterpreted level quickly diverges and never recovers! v ref vi n 0 Overlap can be digitally corrected (without training!) 294 of 561

8 Pipelined ADC - error correction Increase the number of stages and reduce overlap, i.e., decrease the scaling factor, 2 n. Now, less likely to diverge and is able to recover. v ref vi n 0 More stages are required, but typically worth it 295 of 561

9 Pipelined ADC - error correction cont'd Trivial circuitry to retrieve the most likely code! v ref 0 0 vi n v i n t 296 of 561

10 PADC: Taking a look at the subcomponents Sample-and-hold Sub-ADC vi n t 2 vi n n T n S/H n T Sub-DAC Adder Multiplier n-bit ADC n-bit DAC w i n n T D N,, m of 561

11 Sample-and-hold process The input should be sampled and held to reduce the jitter in the subcomponents. Inherent delays will otherwise cause mismatch. Jitter (interdelay) is a very strong limitation on obtainable performance t =n T a t a n T S/H at input of ADC must have full accuracy!!! 298 of 561

12 Sample-and-hold, 1st-level implementation Passive sampling Limitations Clock-feedthrough Charge-injection On-resistance Distortion Jitter Noise t v 1 t v 2 n T CH 299 of 561

13 Sample-and-hold charge injection Channel charge injection W L C ox V V T V 2 nt V 2 nt ~ CH t v 1 t Large capacitor is good! v 2 n T CH Force the delta voltage to always be lower than the LSB voltage: W L C ox CH V ref W L 2C H 2 C ox 2 N 1 3 of 561

14 Sample-and-hold clock feedthrough Clock feed-through C ol V 2 nt = V V 2 nt CH t v 1 t v 2 n T such that C ol C ol V 2 nt =V 1 nt 1 V CH CH T CH Large capacitor is good! Force the delta voltage to always be lower than the LSB voltage: C ol CH V ref C ol N 1 CH of 561

15 Sample-and-hold bandwidth Non-zero resistance t G on = V phi V T V 1 nt Bandwidth limitation, but also distortion due to signal-dependent resistance v1 t v2 nt CH Large capacitor is bad! For a full-scale step at the input, we should settle within 1 LSB accuracy, i.e. V ref e G on 2C H f s G on 0.5 ln 2 N 1 ln 2 Ron 2 2 C H f s C H f s N of 561

16 Noise Given by the bandwidth and the brickwall pole v 2 n, tot kt = CH t v1 t Large capacitor is good! v2 n T CH Quantization noise should be larger than noise, i.e. v 2 n, tot 22 N 2 C H 12 k T 2 12 V ref 303 of 561

17 Sub-ADC V ref Most likely a flash ADC Rr V in Fastest and best choice for low number of bits Use a resistive divider to create reference voltages Offset and matching of resistors must match the accuracy of the active pipeline stage Mismatch information will give requirements on transistors and resistor sizes Rr Rr Relative error is inversely dependent on the area Rr 304 of 561

18 Sub-DAC V ref Reuse the resistive divider for the sub DAC! V i n nt Rr t M n t 4 n Notice that the picture does not display the correct decoding of the t_i bits for control of the DAC switches. (A thermometer-to-walking-one converter consisting of a bank of XOR gates is needed.) Rr t 3 n Rr t 2 n Rr t 1 n w n T 305 of 561

19 Adder/gain V ref Rr V i n nt R 2n R t M n w n T R nt t 4 n A rather compact design can be obtained reusing and combining difference active and passive components. Rr t 3 n Rr t 2 n Rr t 1 n By flipping the t_k bits, we can create the negative version of w(nt) (!) Inversion at the output is no issue, since we can reorder the comparators in the next stage. Encoding not shown 306 of 561

20 Resistance is futile... Why? Noise and OTA design Go for capacitor-based circuits Switched-capacitor comparators in the sub ADC Switched-capacitor DAC Switched-capacitor summation and multiplier 307 of 561

21 Active S/H with offset cancellation Uses bottom-plate sampling to minimize charge feedthrough 2 ' 1 2 v1 t ' 1 C v 2 t 1 v cm v os v1 t v os v1 t C v 2 t v 2 t C v cm v cm v 2=v 1 v os, i.e., offset sensitive, but output is buffered and isolated. 308 of 561

22 Comparators A comparator is not an OP! Consider speed vs. gain A0 A0 1 A s = = 1 s/ p1 p1 ug vs three-stage example 3 A ' s = A' 0 1 s/ p' 1 ' =3 3 3 A' /3 =, with A ' 0 = A0 p ' 1 ug 3 A' 0 3 ' = = 2 /3 A0 A0 (Phase margin is not necessarily an issue!) Vin V o ut 309 of 561

23 Comparators, speed vs resolution 1 Characteristic resolution parameter, c_r, is the smallest level that can toggle the output to reliable levels V OH V OL V OH V OL =A0 V IH V IL c r = A0 Assume a first-order system and apply an input step: v out t =V OL A0 v step 1 e c t Apply the smallest possible signal v out t =V OL A0 c r 1 e c t =V OL V OH V OL 1 e t c Check when we pass the mid-level at the output V OH V OL 0.5=1 e = ln 2 v out =V OL =V OL V OH V OL 1 e 2 c c c 3 of 561

24 Comparators, speed vs resolution 2 Assume now that the input step is K times larger: V OH V OL ' v out ' =V OL =V OL V OH V OL K 1 e 2 2K ln ' ' = 1 ln 2 K ' = 2 K 1 0.5=K 1 e 2 K 1 ln 2 2 K ln 2 c c c If K goes towards infinity, the delay goes towards 0. The more accuracy, the lower sample frequency! 3 of 561

25 Comparators, offset "cancellation" 1 The sub ADC takes sampled input and reference at two different phases: V ref, k ref ref First reference is selected q ref =C V ref, k V 2 ref v i n n T v 2 t C i n v os where A V 2 ref =v os 1 A Then signal is selected and charge must be preserved V 2 i n A q i n =C v i n i n v os = q ref =C V ref, k v os A 1 A A V 2 i n = A v i n i n V ref, k v os (no amplified offset) 1 A 312 of 561

26 Comparators, offset cancellation in OTA Correlated double sampling First phase C2 q1=c 1 v1 v os 1 q2=c 2 0 v os Second phase q1= C 1 v os q2=c 2 v 2 v os 1 2 C1 v1 t 1 2 v os v 2 t Total charge is preserved v2 C 1 [OFFSET CANCELLED] C 1 v 1 v os C 2 v os = C 1 v os C 2 v 2 v os = v1 C of 561

27 Comparators, structure Use (low-gain) preamplifiers and then high-speed positive-feedback latch, which has infinite (DC) gain (time/gain trade-off) Preamplifier section of different kinds A1, 1 A 2, 1 latch v out t A k, 1 latch gm l ~, A l = Cp V OH vi n V ref, k V OL 314 of 561

28 MDAC, concept Combines the sub-dac, adder, gain, and sample-and-hold 2 S/H n S/H n-bit ADC n-bit DAC Combined into one SC MDAC 315 of 561

29 MDAC, SC implementation Bits b i from the ADC (in the 5-bit example below they are binary) 1 C5 b4 C4 b3 C3 b2 C2 b1 C1 b0 C0 k 1 n T 1 2 k n T / v i n 1 Vre f Left as exercise to prove operation of 561

30 Pipelined ADC, conclusions Compact SC solution Pipeline stage C C5 C1 v1 t 1 b4 2 v os v 2 t C4 b3 C3 b2 C2 b1 C1 C0 k 1 n T 1 b0 2 k n T / v i n 1 V ref Vre f V i n nt Rr t 4 n Preamplifier section of different kinds Rr t 3 n A1, 1 A2, 1 latch v out t Ak, 1 latch Rr t 2 n Rr t 1 n 317 of 561

31 What did we do today? Looked at a pipelined ADC as design example Suggested a compact, resistive structure Described an error correction technique Outlined some examples on limiting factors on performance Outlined an offset cancellation technique for comparators Outlined a switched-capacitor architecture 318 of 561

32 What will we do next time? Exam... Download pages 319 of 561