ADC Bit, 50MHz Video A/D Converter

Transcription

1 ADC- -Bit, 0MHz Video A/D Converter FEATURES Low power dissipation (0mW max.) Input signal bandwith (00MHz) Optional synchronized clamp function Low input capacitance (pf typ.) +V or +V /+.V power supply operation Differential nonlinearity (±½LSB max.) Optional self-biased reference CMOS/TTL compatible inputs Outputs -state TTL compatible Surface mount package PRODUCT OVERVIEW The ADC- is an -bit, high speed, monolithic CMOS, sub-ranging A/D converter. The ADC- achieves a sampling rate comparable to fl ash converters by employing a sub-ran single +V or dual +V and +.V power source to allow easy interfacing with.v logic. An optional synchronous clamp function useful for video signal processing is provided. The ADC- is well suited for the portable video signal processors due to its low mw typical power dissipation. The ADC- also features ±0. LSB max. differential non-linearity, a self bias function that can eliminate the need for external references, SNR with THD of db, a small -pin QFP package and an operating temperature range of 0 to + C INPUT/OUTPUT CONNECTIONS Pin Function Pin Function BIT (LSB) NO CONNECTION BIT DIGITAL GROUND (DGND) BIT 0 OUTPUT ENABLE (OE) BIT CLAMP ENABLE (CLE) BIT DIGITAL GROUND (DGND) BIT CLAMP CONTROL (COP) BIT CLAMP REF. (VREF) BIT (MSB) REF. BOTTOM SENSE (VRBS) TEST REF. BOTTOM (VRB) 0 +DVS (Digital) ANALOG GROUND () TEST ANALOG GROUND () ANALOG IN (VIN) NO CONNECTION +AVS (Analog) NO CONNECTION +AVS (Analog) CLAMP IN (CLP) REF. TOP (VRT) +AVS (Analog) REF. TOP SENSE (VRTS) +AVS 0 OUTPUT ENABLE VRTS VRT +AVS +AVS Reference Supply A -Bit Lower Sampling Comparator B A -Bit Lower Encoder B Lower Data Latch DGND BIT (LSB) BIT BIT BIT VIN VRB Clock Generator -Bit Upper Sampling Comparator -Bit Upper Encoder Upper Data Latch BIT BIT BIT BIT (MSB) VRBS VREF + D-FF CLAMP IN DGND TEST (Open) CLAMP CONTROL CLAMP ENABLE 0 +DVS TEST (Open) Figure. ADC- Functional Block Diagram DATEL Cabot Boulevard, Mansfield, MA 0- USA Tel: (0) help@datel.com Mar ADC-.B0 Page of

2 ADC- -Bit, 0MHz Video A/D Converter ABSOLUTE MAXIMUM RATINGS (TA = + C) PARAMETERS LIMITS UNITS Power Supply Voltage (+AVS, +DVS) 0. to Volts Analog Input Voltage, (VIN) 0. to +AVS + 0. Volts Reference Input Voltage (VRT, VRB) 0. to +AVS + 0. Volts Digital Input Voltage (VIH, VIL) 0. to +AVS + 0. Volts Digital Output Voltage (VOH, VOL) 0. to +DVS + 0. Volts FUNCTIONAL SPECIFICATIONS Typical at TA = C, VRT = +.V, VRB = +0.V, +AVS = +V, +DVS = +V to +.V, unless otherwise specified. ANALOG INPUTS MIN. TYP. MAX. UNITS Input Voltage Range Volts Input Capacitance (@ VIN = +.Vdc +0.0VRMS) pf Input Signal Bandwidth db (@ RIN = ) 0 MHz db (@ RIN = ) 00 MHz REFERENCE INPUTS DIGITAL OUTPUTS (continued) MIN. TYP. MAX. UNITS (OE = 0V, CL = pf) (@ +DVS = +V) t PLH...0 ns t PHL...0 ns (@+DVS = +.V) t PLH... ns t PHL... ns -State Output Enable Time (RL = k, CL = pf) (@ +DVS = +V) t PZH...0 ns t PZL..0.0 ns (@+DVS = +.V) t PZH ns t PZL ns -State Output Disable Time (RL = k, CL = pf) (@+DVS = +V) t PHZ, t PLZ... ns (@+DVS = +.V) t PHZ, t PLZ...0 ns CLAM CIRCUIT Clamp Offset Voltage 0 0 mv Clamp Pulse Width... μa PERFORMANCE Reference Resistance VRT VRB 0 0 Reference Current... ma Reference Voltage VRT +. Volts VRB 0 Volts VRT VRB. Volts Self Bias Voltage VRB Volts VRT VRB.0..0 Volts Capacitance (VRT, VRTS, VRB, VRBS) pf Offset Voltage VRT mv VRB 0 0 mv DIGITAL INPUTS Logic Levels Input Voltage "". Volts Input Voltage "0" +0. Volts Input Current A/D CLK 0 0 μa CLP, CLE 0 0 μa OE 0 0 μa Input Capacitance pf A/D Clock Pulse Width (tpw) 0 ns (tpw0) 0 ns DIGITAL OUTPUTS MIN. TYP. MAX. UNITS Output Current (OE = 0V) (@ +DVS = +V) "" ma "0" ma Output Current (OE = 0V) (@ +DVS = +.V) "". ma "0". ma Output Current (@ OE = +V) "" 0 0 A "0" 0 0 A Capacitance pf Footnotes: See technical note Pin tied to and pin tied to +AVS +AVS = +. to +.V and +DVS = to +.V, full operating tem. range. VIL = 0V and VIH = +AVS, full operating temp. range VOH = +DVS 0.V and VOL = +0.V, full operating temp. range Resolution Bit Sampling Rate, maximum, FS 0 MHz minimum, FS 0. MHz Aperature Delay (Tds) 0 ns Integral Linearity Error ±0. ±. LSB Diff. Linearity Error ±0. ±0. LSB Diff. Gain Error % Diff. Phase Error. deg S/N Ratio with THD (fin = 00kHz) db (fin = 00kHz) db (fin = MHz) db (fin = MHz) db (fin = 0MHz) db (fin = MHz) db Spurious Free Dynamic Range (fin = 00kHz) db (fin = 00kHz) db (fin = MHz) db (fin = MHz) db (fin = 0MHz) db (fin = MHz) db POWER REQUIREMENTS +DVS = + to +.V, full operating temp. range OE: + to 0V change OE: 0 to +V change.μs clamp pulse width,.mhz sampling,.khz clamping rate Power Supply +AVS Volts +DVS Volts DGND 0 00 mw Power Supply Current. AIS, DIS (@ +DVS = +V) ma. AIS ma DIS (@ +DVS = +.V) ma Power Dissipation 0 mw ENVIRONMENTAL/PHYSICAL Operating Temp. Range, Case 0 + C Storage Temperature Range +0 C Package Type -pin, plastic QFP Weight 0.00 ounces (0. grams) The clamp pulse width given is for NTSC. For other processing systems adjust the rate to the clamp pulse cycle (/.khz for NTSC) to equal the value for NTSC. NTSC 0IRE ramp,.mhz sampling 0MHz sampling, +AVS = +V DATEL Cabot Boulevard, Mansfield, MA 0- USA Tel: (0) help@datel.com Mar ADC-.B0 Page of

3 ADC- -Bit, 0MHz Video A/D Converter TECHNICAL NOTES. The ADC- is a monolithic CMOS device. It should be handled carefully to prevent static charge pickup.. It has separate power supply terminals +AVS (pins, and ) and +DVS (pin 0) for the internal analog and digital circuits. It is recommended that both +AVS and +DVS be powered from a single source Other external digital circuits must be powered with a separate +DVS. A time lag between the two power supplies could induce latch up when power is turned on if separate supplies are used. The operating range of +DVS is from +.0V to +.V and it allows the use of a common power supply with.v digital systems. The +.V power for +DVS in this case should be taken or derived from the +AVS supply to avoid latch up. No power supply terminal should be left open.. The ADC- has separate grounds, the analog GND (pins and ) and digital GND (pins and ). Separate and substantial and DGND ground planes are required. These grounds have to be connected to one earth point underneath the device. Digital returns should not flow through analog grounds. Connect all ground lines to the power point.. Bypass all power lines to GND with 0. F ceramic chip capacitors as close to the device as possible. This is very important.. Even though the analog input capacitance is a low pf, it is recommended that high frequency input be provided via a high-speed buffer amplifier. A parasitic oscillation may be generated when a high-speed amplifier is used. A ohm resistor inserted between the output of an amplifier and the analog input of the ADC- will improve the situation. Kick back noise from pulses will be observed at the analog input terminal, but this has no influence on the ADC- performance.. Apply +.V to VRT (pin, reference top) and 0.V to VRB (pin reference bottom) to obtain an analog input range of +0.V to +.V. Conversion accuracy is dependent on stable reference voltages. Provide reference inputs via amplifiers that have enough driving power to avoid noise problems. Keep to the following equations; 0V VRB VRT +.V, VRT VRB.V The ADC- has a self bias function which allows the device to work without external references. Connect VRTS (pin, self bias top) to +AVS and VRBS (pin, self bias bottom) to the analog GND to obtain an analog input range of +0. to +.V. Typical voltages at VRT (pin ) and VRB (pin ) will then be +.V and +0.V respectively. Under an application where this self bias function is used, the effects of temperature changes are minimal. Voltage changes of the +V supply have direct influence on the performance of the device. The use of external references is recommended for applications sensitive to gain error, no ac signals can be used as references for this device.. A voltage up to +AVS + 0.V can be applied to each digital input even when +.V is powered to +DVS, but the digital output voltage never exceeds +DVS.. Layout pulse input (pin ) as short as possible for minimum influence on other signals. Use of a 00 ohm series resistor is recommended to protect the device as there may be some voltage difference and turn-on-time lag on the power supplies. Analog inputs signals are sampled at the falling edge of an pulse and digital data become available at the rising edge of an pulse that is delayed by. clock cycles. The are positive pulse that have 0% duty cycle. The minimum clock pulse width is 0 nsec for both high and low levels. Keep it low level while A/D conversions are on hold.. Digital output is -state. To enable -state outputs connect the OUTPUT ENABLE (pin 0) to GND. To disable, connect it to +DVS. The output is recommended to be latched and buffered through output registers. The device may be damaged if a voltage higher than +DVS + 0.V is given to digital output pins while at high impedance level. 0. The 0MHz sampling rate is guaranteed. It is not recommended to use this device at sampling rates slower than 00kHz because the droop characteristics of the internal sample and hold exceed the limit required to maintain the specified accuracy of the device. Also, burst mode sampling is not recommended.. The ADC- has a clamp function. This clamp is enabled when CLAMP ENABLE (pin ) is tied to GND and is disabled when tied to +DVS or left open. Clamp pulse inputs (pin ) are effective when this clamp function is enabled and signals are clamped whole, this clamp pulse is low. The clamp reference input (pin ) is set by an external trim. The CCP terminal (pin ) integrates the clamp control voltage across an external capacitor. Refer to Figure for examples of various ways to use this clamp function.. The TEST and (pins and ) are not used. Always leave them open. DATEL Cabot Boulevard, Mansfield, MA 0- USA Tel: (0) help@datel.com Mar ADC-.B0 Page of

4 ADC- -Bit, 0MHz Video A/D Converter THEORY OF OPERATION (See Functional Block Diagram, Figure, and Timing Diagrams, Figure ). The DATEL ADC- is a -step parallel A/D converter featuring a -bit upper comparator group and two -bit lower comparator groups, each with built-in sample and hold. A reference voltage equal to the voltage between (VRT VRB)/ is constantly applied to the -bit upper comparator block. A voltage corresponding to the upper data is fed through the reference supply to the lower data. VRTS and VRBS pins provde the self generation function for VRT (reference voltage top) and VRB (reference voltage bottom) voltages.. This converter uses an offset cancelation type comparator and operates synchronously with the external clock. It features various operating modes which are shown in the Timing Diagram (Figure ) by the symbols S, H and C. These characters stand for Input Sampling (Auto Zero) Mode, Input Hold Mode and Comparison Mode.. The operation of the respective parts is as indicated in Figure -. For instance, input voltage N is sampled with the falling edge of the first clock by means of the upper comparator block and the lower comparator A block. Input voltage N+ is sampled with the falling edge of the second clock by means of the upper comparator block and lower comparator B block. The upper comparator block finalizes comparison data UD(N) with the rising edge of the second clock. The lower comparator block finalizes comparison data LD(N) with the rising edge of the third clock. UD(N) and LD(N) are combined and routed to the output as Output Data N with the rising edge of the fourth clock. Thus there is a. clock delay from the analog input sampling point to the digital data output. Table : Digital Output Coding OUTPUT CODE VIN MSB LSB 0V mv V V V V tr =.ns tr =.ns 0% V OE INPUT.V 0% 0V tplz tpzl VOH OUTPUT.V 0% VOL/(=DGND) OUTPUT tphz 0% tpzh.v VOH/(=DGND) VOL Figure -. ADC- Timing Diagram tr = ns tf = ns 0% V CLOCK.V 0% 0V DATA OUTPUTS 0. DVS 0. DVS tplh tphl Figure -. ADC- Timing Diagram DATEL Cabot Boulevard, Mansfield, MA 0- USA Tel: (0) help@datel.com Mar ADC-.B0 Page of

5 ADC- -Bit, 0MHz Video A/D Converter Tds 0ns typ. N N+ ANALOG SIGNAL TPW TPW0 N+ N+ 0ns min. 0ns min. CLOCK.V TPLH TPHL DATA OUTPUTS N N N N UPPER SAMPLING COMPARTOR S (N) C (N) S (N+) C (N+) S (N+) C (N+) S (N+) C (N+) UPPER OUTPUT DATA UD (N ) UD (N) UD (N+) UD (N+) LOWER SAMPLING COMPARTOR S (N) H (N) C (N) S (N+) H (N+) C (N+) LOWER OUTPUT DATA LD (N ) LD (N) LOWER SAMPLING COMPARTOR H (N ) C (N ) S (N+) H (N+) C (N+) S (N+) H (N+) LOWER OUTPUT DATA LD (N ) LD (N ) LD (N+) S = Sample Mode, H = Hold Mode, C = Comparate Mode Internal Operation of the ADC- Figure -. ADC- Timing Diagram 0. F 0. F 0. F HC0 F 0. F 0. F +V (D) +V +V 0 H F ANALOG IN F 0 F 0. F 0 k 00 k F 00 k +V V 0. F 0. F 0. F 0pF 0. F 0 ADC- 0 BIT (MSB) BIT BIT BIT BIT BIT BIT BIT (LSB) F 0. F V k k 0 H V 00 Figure. Typical Connection Diagram DATEL Cabot Boulevard, Mansfield, MA 0- USA Tel: (0) help@datel.com Mar ADC-.B0 Page of

6 ADC- -Bit, 0MHz Video A/D Converter CLAMP PULSE +V (D) +V (D) 0 0 VRT ANALOG IN 0pF ANALOG IN 0 F 0pF 0 VRB 0 k 0.0 F Figure -. Clamp Not Used in Self Bias Mode Figure -. Clamp Used in External Reference Mode CLAMP PULSE +V (D) +V (D) ANALOG IN 0 F 0pF 0 0 ANALOG IN 0 F 0pF 0 0 Comparator Clamp Level Data k 0.0 F 0.0 F D/A Figure -. Clamp Used in Self Bias Mode Figure -. Digital Clamp Used in Self Bias Mode +.V (D) CLAMP PULSE 0 ANALOG IN 0 F 0pF 0 k 0.0 F Figure -. Clamp Used in Self Bias Mode With +V/+.V Dual Power Supply DATEL Cabot Boulevard, Mansfield, MA 0- USA Tel: (0) help@datel.com Mar ADC-.B0 Page of

7 ADC- -Bit, 0MHz Video A/D Converter Sampling Delay Analog Input Bandwidth Analog Input Frequency vs. S/N + THD, Effective Bit Sampling Delay (ns) 0 AVS = DVS = V Output Level (db) 0 Sine wave Vp-p input AVS = DVS +V TA = C Effective Bit (db) SNR (db) AVS = DVS = V VIN = Vp-p TA = C Analog Input Frequency (MHz) Analog Input Frequency (MHz) 0 Analog Input Frequency vs. FSDR FSDR (db) AVS = DVS = V VIN = Vp-p TA = C (ns) 0 AVS = DVS +V CL = pf (ns) 0 AVS = DVS +V CL = pf Analog Input Frequency (MHz) Load Capacitance vs. Load Capacitance vs. (ns) 0 AVS = DVS +V CL = pf (ns) 0 FS = 0MHz AVS = +V DVS = +.V TA = C (ns) 0 FS = 0MHz +AVS = +V TA = C Load Capacitance (pf) Load Capacitance (pf) Supply Current Supply Voltage vs. Supply Current Sampling Rate vs. Supply Current Supply Current (ma) AVS = DVS = +V Supply Current (ma) AVS = DVS TA = C Supply Current (ma) AVS = DVS = +V Supply Voltage (V) Sampling Frequency (MHz) Input Frequency vs. Supply Current Max. Sampling Rate Supply Voltage vs. Sampling Rate Supply Current (ma) 0 Sine wave.vp-p AVS = DVS = +V TA = C Max. Sampling Rate (MHz) 0 0 fin = khz, triangular wave input AVS = DVS +V Sampling Rate (MHz) AVS = DVS Input Frequency (MHz) Supply Voltage (V) Figure : Typical Performance Curves DATEL Cabot Boulevard, Mansfield, MA 0- USA Tel: (0) help@datel.com Mar ADC-.B0 Page of

8 ADC- -Bit, 0MHz Video A/D Converter DIGITAL OUTPUT ANALOG INPUT REFERENCE INPUT +DV S V RTS V RB to V RT R ref RB V RBS DGND CLAMP REFERENCE VOLTAGE INPUT (VREF) CLAMP CONTROL VOLTAGE (CCP) OUTPUT ENABLE (OE) CLAMP PULSE INPUT (CLP) CLAMP ENABLE (CLE) 0 Figure : Equivalent Circuits 0. ±0.00 (.0 ±0.) 0. ±0.00 (. ±0.) MECHANNICAL DIMENSIONS INCHES (mm) 0.0 (0.) 0.0 ±0.00 (0.0 0., +0.) 0.0 (0.) 0. (.0) 0.0 ±0.00 (. ±0.) 0.00 ±0.00 (0. ±0.) 0 to ±0.00 (0. ±0.0) ORDERING INFORMATION ADC- -bit, 0MHz A/D converter DATEL Cabot Boulevard, Mansfield, MA 0- USA ITAR and ISO 00/00 REGISTERED help@datel.com. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifi cations are subject to change without notice. Mar ADC-.B0 Page of