SN54HC682, SN74HC682 8-BIT MAGNITUDE COMPARATORS

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1 SCLS0C MARCH 9 REVISED MAY 99 Compare Two -Bit Words 00-kΩ Pullup Resistors Are on the Q Inputs Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These magnitude comparators perform comparisons of two -bit binary or BCD words. The HC2 feature 00-kΩ pullup termination resistors on the Q inputs for analog or switch data. The SNHC2 is characterized for operation over the full military temperature range of C to 2 C. The SNHC2 is characterized for operation from 0 C to C. SNHC2...J OR W PACKAGE SNHC2... DW OR N PACKAGE (TOP VIEW) P > Q P Q P Q GND SNHC2... FK PACKAGE (TOP VIEW) P > Q V CC P = Q V CC P = Q Q P Q P Q P FUNCTION TABLE DATA OUTPUTS INPUTS P, Q P = Q P > Q P = Q L H P > Q H L P < Q H H The P < Q function can be generated by applying P = Q and P > Q to a 2-input NAND gate. P Q P Q GND P Q P Q P Q Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 99, Texas Instruments Incorporated POST OFFICE BOX 0 DALLAS, TEXAS 2

2 SCLS0C MARCH 9 REVISED MAY 99 logic symbol 2 COMP 0 P P 9 P P = Q P P P 0 Q 9 Q 2 Q P > Q Q Q Q P = Q P > Q This symbol is in accordance with ANSI/IEEE Std 9-9 and IEC Publication POST OFFICE BOX 0 DALLAS, TEXAS 2

3 SCLS0C MARCH 9 REVISED MAY 99 logic diagram (positive logic) 9 P=Q 2 P Q P Q 9 P 2 P>Q Q P Q P Q POST OFFICE BOX 0 DALLAS, TEXAS 2

4 SCLS0C MARCH 9 REVISED MAY 99 absolute maximum ratings over operating free-air temperature range Supply voltage range, V CC V to V Input clamp current, I IK (V I < 0 or V I > V CC ) (see Note ) ±20 ma Output clamp current, I OK (V O < 0 or V O > V CC ) (see Note ) ±20 ma Continuous output current, I O (V O = 0 to V CC ) ±2 ma Continuous current through V CC or GND ±0 ma DW package C/W N package C/W Storage temperature range, T stg C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD, except for through-hole packages, which use a trace length of zero. recommended operating conditions SNHC2 SNHC2 UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 2 2 V VCC = 2 V.. VIH High-level input voltage VCC =. V.. V VCC = V.2.2 VCC = 2 V VIL Low-level input voltage VCC =. V V VCC = V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V tt Input transition (rise and fall) time VCC =. V ns VCC = V TA Operating free-air temperature 2 0 C PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 0 DALLAS, TEXAS 2

5 SCLS0C MARCH 9 REVISED MAY 99 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 2 C SNHC2 SNHC2 MIN TYP MAX MIN MAX MIN MAX 2 V IOH = 20 µa. V VOH VI = VIH or VIL V V IOH = ma. V.9... IOH =.2 ma V V IOL = 20 µa. V VOL VI = VIH or VIL V V IOL = ma. V IOL =.2 ma V IIH VI = VCC V na IIL VI =0 Q inputs V µa All other inputs V na ICC VI = VCC or 0, IO = 0 V µa Ci 2 V to V pf UNIT switching characteristics over recommended operating free-air temperature range, C L = 0 pf (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 2 C SNHC2 SNHC2 MIN TYP MAX MIN MAX MIN MAX 2 V 0 2 tpd P or Q Any. V 2 9 ns V V 0 9 tt Any. V 22 9 ns V 9 UNIT operating characteristics, T A = 2 C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load 0 pf PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 0 DALLAS, TEXAS 2

6 SCLS0C MARCH 9 REVISED MAY 99 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point CL = 0 pf (see Note A) Input tplh tphl VCC 0 V LOAD CIRCUIT In-Phase Output 0% 90% 90% tr VOH 0% VOL tf Input 0% 90% 90% tr VCC 0% 0 V tf Out-of-Phase Output tphl 90% 0% 0% tf tplh VOH 90% VOL tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 0 Ω, tr = ns, tf = ns. C. The outputs are measured one at a time with one input transition per measurement. D. tplh and tphl are the same as tpd. Figure. Load Circuit and Voltage Waveforms POST OFFICE BOX 0 DALLAS, TEXAS 2

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