MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop

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MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop General Description The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology.

Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system.

1 MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop General Description The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity and low power coumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. These devices are positive edge triggered flip-flops. Data at the D inputs, meeting the set-up and hold time requirements, are traferred to the Q outputs on positive going traitio of the CLOCK (CK) input. When a high logic level is applied to the OUTPUT CONTROL (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The 74HC logic family is speed, function, and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to CC and ground. Ordering Code: Features September 1983 Revised May 2005 Typical propagation delay: 18 Wide operating voltage range: 2 6 Low input current: 1 PA maximum Low quiescent current: 80 PA maximum Compatible with bus-oriented systems Output drive capability: 15 LS-TTL loads MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop Order Number Package Number Package Description MM74HC574WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide MM74HC574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC574N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP, SOIC, SOP and TSSOP Output Clock Data Output Control L n H H L n L L L L X Q 0 H X X Z H HIGH Level L LOW Level X Don't Care n Traition from LOW-to-HIGH Z High Impedance State Q 0 The level of the output before steady state input conditio were established Top iew 2005 Fairchild Semiconductor Corporation DS

2 MM74HC574 Absolute Maximum Ratings(Note 1) (Note 2) Supply oltage ( CC ) 0.5 to 7.0 DC Input oltage ( IN ) 1.5 to CC 1.5 DC Output oltage ( OUT ) 0.5 to CC 0.5 Clamp Diode Current (I IK, I OK ) r20 ma DC Output Current, per pin (I OUT ) r35 ma DC CC or GND Current, per pin (I CC ) r70 ma Storage Temperature Range (T STG ) 65qC to 150qC Power Dissipation (P D ) (Note 3) 600 mw S.O. Package only 500 mw Lead Temperature (T L ) (Soldering 10 seconds) 260qC Recommended Operating Conditio Min Max Units Supply oltage ( CC ) 2 6 DC Input or Output oltage 0 CC ( IN, OUT ) Operating Temperature Range (T A ) qc Input Rise or Fall Times (t r, t f ) CC CC CC Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating plastic N package: 12 mw/qc from 65qC to 85qC. DC Electrical Characteristics (Note 4) Symbol Parameter Conditio CC T A 25qC T A 40 to 85qC T A 55 to 125qC Units Typ Guaranteed Limits IH Minimum HIGH Level Input oltage IL Maximum LOW Level Input oltage OH Minimum HIGH Level Output IN IH or IL oltage I OUT d 20 PA IN IH or IL I OUT d 6.0 ma I OUT d 7.8 ma OL Maximum LOW Level Output IN IH or IL oltage I OUT d 20 PA IN IH or IL I OUT d 6.0 ma I OUT d 7.8 ma I IN Maximum Input Current IN CC or GND 6.0 r0.1 r1.0 r1.0 PA I OZ Maximum 3-STATE OUT CC or GND Output Leakage Current OC IH 6.0 r0.5 r5.0 r10 PA I CC Maximum Quiescent Supply IN CC or GND Current I OUT 0 PA PA 'I CC Quiescent Supply Current CC 5.5 OE per Input Pin IN 2.4 CLK ma or 0.4 (Note 4) DATA Note 4: For a power supply of 5 r10% the worst-case output voltages ( OH, and OL ) occur for HC at 4.5. Thus the 4.5 values should be used when designing with this supply. Worst-case IH and IL occur at CC 5.5 and 4.5 respectively. (The IH value at 5.5 is 3.85.) The worst-case leakage current (I IN, I CC, and I OZ ) occur for CMOS at the higher voltage and so the 6.0 values should be used. 2

3 AC Electrical Characteristics CC 5, T A 25qC, t r t f 6 Guaranteed Symbol Parameter Conditio Typ Limit Units f MAX Maximum Operating Frequency MHz t PHL, t PLH Maximum Propagation Delay, Clock to Q C L 45 pf t PZH, t PZL Maximum Output Enable Time R L 1 k: C L 45 pf t PHZ, t PLZ Maximum Output Disable Time R L 1 k: C L 5 pf t S Minimum Setup Time, Data to Clock t H Minimum Hold Time, Clock to Data 3 5 t W Minimum Pulse Clock Width 8 15 MM74HC574 AC Electrical Characteristics CC , C L 50 pf, t r t f 6 (unless otherwise specified) Symbol Parameter Conditio CC T A 25qC T A 40 to 85qC T A 55 to 125qC Units Typ Guaranteed Limits f MAX Maximum Operating Frequency C L 50 pf MHz t PHL, t PLH Maximum Propagation C L 50 pf Delay, Clock to Q C L 150 pf C L 50 pf C L 150 pf C L 50 pf C L 150 pf t PZH, t PZL Maximum Output Enable R L 1 k: Time C L 50 pf C L 150 pf C L 50 pf C L 150 pf C L 50 pf C L 150 pf t PHZ, t PLZ Maximum Output Disable Time R L 1 k: C L 50 pf t S Minimum Setup Time Data to Clock t H Minimum Hold Time Clock to Data t THL, t TLH Maximum Output Rise C L 50 pf and Fall Time t W Minimum Clock Pulse Width t r,t f Maximum Clock Input Rise and Fall Time C PD Power Dissipation Capacitance OC CC 5 (Note 5) (per latch) OC GND 58 pf C IN Maximum Input Capacitance pf 3

4 MM74HC574 AC Electrical Characteristics (Continued) Symbol Parameter Conditio CC T A 25qC T A 40 to 85qC T A 55 to 125qC Units Typ Guaranteed Limits C OUT Maximum Output pf Capacitance Note 5: C PD determines the no load dynamic power coumption, P D C PD 2 CC f I CC CC, and the no load dynamic current coumption, I S C PD CC f I CC. 4

Physical Dimeio inches (millimeters) unless otherwise noted MM74HC574 20-Lead Small Outline

5 Physical Dimeio inches (millimeters) unless otherwise noted MM74HC Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5

6 MM74HC574 Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 6

Physical Dimeio inches (millimeters) unless otherwise noted (Continued) MM74HC574 20-Lead Thin

7 Physical Dimeio inches (millimeters) unless otherwise noted (Continued) MM74HC Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7

MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.

8 MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any respoibility for use of any circuitry described, no circuit patent licees are implied and Fairchild reserves the right at any time without notice to change said circuitry and specificatio. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with itructio for use provided in the labeling, can be reasonably expected to result in a significant injury to the user A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

MM74HC374 3-STATE Octal D-Type Flip-Flop

MM74HC374 3-STATE Octal D-Type Flip-Flop 3-STATE Octal D-Type Flip-Flop General Description The MM74HC374 high speed Octal D-Type Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption