PO54G74A, PO74G74A. Pin Configuration. Logic Block Diagram. Pin Description. 54, 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION: 1D 2

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1 DUAL POSITIVEEDGETRIGGERED DTYPE FLIPFLOPS FEATURES:. Patented technology. Specified From 0 C to 12 C, C to 12 C. Operating frequency is faster than 600MHz. VCC Operates from 1.6V to 3.6V. Propagation delay < 2 max with 1pf load. Low input capacitance: pf typical. LatchUp Performance Exceeds 20 ma Per JESD 17. ESD Protection Exceeds JESD VHumanBodyModel (A11A). 200VMachineModel (A11A). Available in 1pin 10mil wide SOIC package. Available in 1pin Ceramic Dual Flatpack. Available in 20pin Leadless Ceramic Chip Carrier DESCRIPTION: Potato Semiconductor s PO7G7A is designed for world top performance using submicron CMOS technology to achieve higher than 600MHz TTL /CMOS output frequency with less than 2 propagation delay. This dual D flipflop is designed for 1.6V to 3.6V VCC operation. Inputs can be driven from either 3.3V or V devices. This feature allows the use of these devices as tralators in a mixed 3.3V/V system environment. Pin Configuration 1CLR 1 1 V CC 1D 1CLR V CC 2CLR 1D 1CLK 1PRE CLR 2D 2CLK 2PRE 1CLK 1PRE D 2CLK 2PRE GND 7 8 GND Pin Description INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X L L H H H H L H H L L H H H L X Q 0 Q 0 Logic Block Diagram 1CLR 1 1 Vcc 1D 2 PRE D Q 13 2CLR 1 1CLK 3 Q CLR 12 2D 1PRE D PRE Q CLK 2PRE 2 6 Q CLR 9 GND /01/10

2 DUAL POSITIVEEDGETRIGGERED DTYPE FLIPFLOPS Maximum Ratings Description Max Unit Storage Temperature 6 to 10 C Operation Temperature to 12 C Operation Voltage 0. to +.6 V Input Voltage 0. to +. V Voltage 0. to Vcc+0. V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description Test Conditio Min Typ Max Unit VOH High voltage Vcc=3V Vin=VIH or VIL, IOH= 12mA 2. 3 V VOL Low voltage Vcc=3V Vin=VIH or VIL, IOH=12mA V VIH Input High voltage Guaranteed Logic HIGH Level (Input Pin) 2. V VIL Input Low voltage Guaranteed Logic LOW Level (Input Pin) V IIH Input High current Vcc = 3.6V and Vin =.V 1 ua IIL Input Low current Vcc = 3.6V and Vin = 0V 1 ua VIK Clamp diode voltage Vcc = Min. And IIN = 18mA V 1. For conditio shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, 2 C ambient. 3. This parameter is guaranteed but not tested.. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.. VoH = Vcc 0.6V at rated current 2 01/01/10

3 DUAL POSITIVEEDGETRIGGERED DTYPE FLIPFLOPS Power Supply Characteristics Symbol Description Test Conditio (1) Min Typ Max Unit IccQ Quiescent Power Supply Current Vcc=Max, Vin=Vcc or GND ua 1. For conditio shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, 2 C ambient. 3. This parameter is guaranteed but not tested.. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Capacitance Parameters (1) Description Test Conditio Typ Unit Cin Input Capacitance Vin = 0V pf Cout Capacitance Vout = 0V 6 pf 1 This parameter is determined by device characterization but not production tested. Switching Characteristics Symbol tsu th tplh tphl tplh tphl Description Setup time before CLK Hold time, data after CLK Propagation Delay CLK to Q or Q Propagation Delay CLK to Q or Q Propagation Delay CLR or PRE to Q or Q Test Conditio (1) CL = 1pF CL = 1pF CL = 1pF Max 2 CL = 1pF 2 tr/tf Rise/Fall Time 0.8V 2.0V 0.8 fmax Propagation Delay CLR or PRE to Q or Q Input Frequency CL=2pF 1pF 600 MHz 1. See test circuits and waveforms. 2. tplh, tphl, tsu, and th are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 00MHz 3 3 Min Unit 3 01/01/10

4 DUAL POSITIVEEDGETRIGGERED DTYPE FLIPFLOPS Test Waveforms t w Timing Input Input Data Input t su t h PULSE DURATION SETUP AND HOLD TIMES Input Control t PLH t PHL V OH V OL Waveform 1 S1 at VLOAD (see Note B) t PZL t PLZ V OL + V V LOAD /2 V OL t PHL t PLH PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS V OH V OL Waveform 2 S1 at GND (see Note B) t PZH t PHZ V OH V ENABLE AND DISABLE TIMES LOW AND HIGHLEVEL ENABLING V OH Test Circuit Vcc Pulse Generator D.U.T 0Ohm 1pF to 2pF 01/01/10

5 DUAL POSITIVEEDGETRIGGERED DTYPE FLIPFLOPS Packaging Mechanical Drawing: 1 pin 10mil SOIC Denotes dimeio in inches Denotes dimeio in millimenters Packaging Mechanical Drawing: 1pin Leadless Ceramic Chip Carrier Denotes dimeio in inches Denotes dimeio in millimenters 01/01/10

6 DUAL POSITIVEEDGETRIGGERED DTYPE FLIPFLOPS Packaging Mechanical Drawing: 20pin Ceramic Dual Flatpack (0,1) (0,2) (2,03) 0.06 (1,63) (0,1) (0,2) 0.0 (1,0) 0.0 (1,1) 0.0 (1,1) 0.03 (0,89) (0,71) (0,) 0.00 (1,27) 0.0 (1,1) 0.03 (0,89) (9,09) 0.32 (8,69) (9,09) (7,80) Denotes dimeio in inches Denotes dimeio in millimenters IC Ordering Information Ordering Code Package TopMarking T A PO7G7ASU for Tube 1pin SOIC Pbfree & Green POTATO7G7AS 0 C to 12 C PO7G7ASR for Tape & Reel 1pin SOIC Pbfree & Green POTATO7G7AS 0 C to 12 C POG7ALU for Tube 1pin Leadless Ceramic Chip Carrier Pbfree & Green POTATOG7AL C to 12 C 20pin Ceramic POG7AFU for Tube Pbfree & Green Dual Flatpack POTATOG7AF C to 12 C IC Package Information PACKAGE CODE PACKAGE TYPE TAPE WIDTH (mm) TAPE PITCH (mm) PIN 1 LOCATION TAPE TRAILER LENGTH QTY PER REEL TAPE LEADER LENGTH S SOIC Top Left Corner 39 (12 ) (20 ) L LCCC 20 N/A N/A N/A N/A N/A N/A F CFP 1 N/A N/A N/A N/A N/A N/A 10 QTY PER TUBE 6 01/01/10

PO3B14A. Description. Truth Table. High Bandwidth Potato Chip V CC N.C. EN EN S 1 A 3 B 3 B 2 A 2 A 1 B 1 Y A Y B GND

PO3B14A. Description. Truth Table. High Bandwidth Potato Chip V CC N.C. EN EN S 1 A 3 B 3 B 2 A 2 A 1 B 1 Y A Y B GND www.potatosemi.com FEATURES: Patented technology High signal -3db passing bandwidth at 1.2GHz Near-Zero propagation delay VCC = 1.65V to 3.6V Ultra-Low Quiescent Power: 0.1 A typical Ideally suited for