8-bit binary counter with output register; 3-state

Transcription

1 Rev March 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary counter features a master reset counter (MRC) and count enable (CE) inputs. The counter and storage register have separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable. A ripple carry output () is provided for cascading. Cascading is accomplished by connecting of the first stage to CE of the second stage. Cascading for larger count chains can be accomplished by connecting of each stage to the counter clock (CPC) input of the following stage. If both clocks are connected together, the counter state always is one count ahead of the register. Counter and register have independent clock inputs Counter has master reset Complies with JEDEC standard no. 7A Multiple package options ESD protection: HBM EIA/JESD22-A114-B exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101C exceeds 2000 V Specified from 40 C to+80 C and from 40 C to +125 C Table 1: Quick reference data GND = 0 V; T amb =25 C; t r =t f =6ns Symbol Parameter Conditions Min Typ Max Unit t PHL, t PLH propagation delay CPC to C L = 50 pf; V CC = 4.5 V ns propagation delay CPR to C L = 50 pf; V CC = 4.5 V ns Qn t PLH propagation delay MRC to C L = 50 pf; V CC = 4.5 V ns t PZH, t PZL 3-state output enable time OE to Qn C L = 50 pf; V CC = 4.5 V ns

2 4. Ordering information Table 1: Quick reference data continued GND = 0 V; T amb =25 C; t r =t f =6ns Symbol Parameter Conditions Min Typ Max Unit t PHZ, t PLZ 3-state output disable time C L = 50 pf; V CC = 4.5 V ns OE to Qn C I input capacitance pf C PD power dissipation capacitance [1] [2] pf [1] C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i N + (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. [2] The condition is V I = GND to V CC. Table 2: Type number Ordering information Package Temperature range Name Description Version D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width SOT mm PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body SOT403-1 width 4.4 mm BQ 40 C to +125 C DHVQFN16 plastic dual-in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body mm SOT763-1 Product data sheet Rev March of 25

3 5. Functional diagram 12 CE CPC MRC 8-BIT BINARY COUNTER 13 CPR 8-BIT STORAGE REGISTER 9 Q0 15 Q1 1 Q OE 3-STATE OUTPUTS Q3 Q4 3 4 Q5 5 Q6 6 Q aac542 Fig 1. Functional diagram 12 CE CPC CPR 9 Q0 15 Q1 1 Q2 2 Q3 3 Q4 4 Q5 5 Q6 6 Q7 7 MRC OE aac OE 13 CPR 12 CE 11 CPC 10 MRC EN3 C2 G1 CTR8 1+ (CT=255)Z4 CT=0 1D 2D 3 2D Q0 1 Q1 2 Q2 3 Q3 4 Q4 5 Q5 6 Q6 7 Q7 001aac545 Fig 2. Logic symbol Fig 3. IEC logic symbol Product data sheet Rev March of 25

4 OE 14 CPR 13 CE 12 CPC 11 9 MRC 10 R T 1R C1 1S 15 Q0 R T 1R C1 1S 1 Q1 R T 1R C1 1S 2 Q2 R T 1R C1 1S 3 Q3 R T 1R C1 1S 4 Q4 R T 1R C1 1S 5 Q5 R T 1R C1 1S 6 Q6 R T 1R C1 1S 7 Q7 001aac543 Fig 4. Logic diagram Product data sheet Rev March of 25

5 6. Pinning information 6.1 Pinning terminal 1 index area 1 Q1 VCC 16 Q Q0 Q1 Q2 Q3 Q4 Q V CC Q0 OE CPR CE Q3 Q4 Q5 Q6 Q GND (1) OE CPR CE CPC MRC Q CPC 8 9 Q7 GND aac564 MRC GND Transparent top view 001aac547 Fig 5. Pin configuration SO16 and TSSOP16 Fig 6. (1) The die substrate is attached to the exposed die pad using conductive die attach material. It can not be used as a supply pin or input. Pin configuration DHVQFN Pin description Table 3: Pin description Symbol Pin Description Q1 1 parallel data output 1 Q2 2 parallel data output 2 Q3 3 parallel data output 3 Q4 4 parallel data output 4 Q5 5 parallel data output 5 Q6 6 parallel data output 6 Q7 7 parallel data output 7 GND 8 ground (0 V) 9 ripple carry output (active LOW) MRC 10 master reset counter input (active LOW) CPC 11 counter clock input (active HIGH) CE 12 count enable input (active LOW) CPR 13 register clock input (active HIGH) OE 14 output enable input (active LOW) Q0 15 parallel data output 0 V CC 16 supply voltage Product data sheet Rev March of 25

6 7. Functional description 7.1 Function table Table 4: Function table [1] [2] Inputs Description OE CPR MRC CE CPC H X X X X Q outputs disable L X X X X Q outputs enable X X X X counter data stored into register X X X X register stage is not changed X X L X X counter clear X X H L advance one count X X H L no count X X H H X no count [1] H = HIGH voltage level L = LOW voltage level X = don t care = LOW-to-HIGH transition = HIGH-to-LOW transition [2] = Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 (Q0 to Q7 are internal outputs of the counter) Product data sheet Rev March of 25

7 CPC CPR MRC CE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 count inhibit counter clear high-impedance OFF-state 001aac548 Fig 7. Typical timing sequence Product data sheet Rev March of 25

8 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input diode current V I < 0.5 V or V I >V CC V - ±20 ma I OK output diode current V O < 0.5 V or V O >V CC V - ±20 ma source or sink output current V O = 0.5 V to V CC V I O standard output - ±25 ma Qn bus driver output - ±35 ma I CC, I GND V CC or GND current - ±70 ma T stg storage temperature C P tot total power dissipation [1] mw [1] For SO16 packages: P tot derates linearly with 8 mw/k above 70 C. For TSSOP16 packages: P tot derates linearly with 5.5 mw/k above 60 C. For DHVQFN16 packages: P tot derates linearly with 8 mw/k above 60 C. 9. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V t r, t f input rise and fall V CC = 2.0 V ns times V CC = 4.5 V ns V CC = 6.0 V ns T amb ambient temperature C Product data sheet Rev March of 25

9 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb =25 C V IH HIGH-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I =V IH or V IL all outputs I O = 20 µa; V CC = 2.0 V V I O = 20 µa; V CC = 4.5 V V I O = 20 µa; V CC = 6.0 V V standard output I O = 4 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V Qn bus driver output I O = 6 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V V OL LOW-level output voltage V I =V IH or V IL all outputs I O =20µA; V CC = 2.0 V V I O =20µA; V CC = 4.5 V V I O =20µA; V CC = 6.0 V V standard output I O = 4 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V Qn bus driver output I O = 6 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V I LI input leakage current V I =V CC or GND; V CC = 6.0 V - - ±0.1 µa I OZ 3-state output OFF-state current V I =V IH or V IL ; V O =V CC or GND; - - ±0.5 µa V CC = 6.0 V I CC quiescent supply current V I =V CC or GND; I O =0A; µa V CC = 6.0 V C I input capacitance pf Product data sheet Rev March of 25

10 Table 7: Static characteristics continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +85 C V IH HIGH-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I =V IH or V IL all outputs I O = 20 µa; V CC = 2.0 V V I O = 20 µa; V CC = 4.5 V V I O = 20 µa; V CC = 6.0 V V standard output I O = 4 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V Qn bus driver output I O = 6 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V V OL LOW-level output voltage V I =V IH or V IL all outputs I O =20µA; V CC = 2.0 V V I O =20µA; V CC = 4.5 V V I O =20µA; V CC = 6.0 V V standard output I O = 4 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V Qn bus driver output I O = 6 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V I LI input leakage current V I =V CC or GND; V CC = 6.0 V - - ±1.0 µa I OZ 3-state output OFF-state current V I =V IH or V IL ; V O =V CC or GND; - - ±5.0 µa V CC = 6.0 V I CC quiescent supply current V I =V CC or GND; I O =0A; V CC = 6.0 V µa Product data sheet Rev March of 25

11 Table 7: Static characteristics continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +125 C V IH HIGH-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I ==V IH or V IL all outputs I O = 20 µa; V CC = 2.0 V V I O = 20 µa; V CC = 4.5 V V I O = 20 µa; V CC = 6.0 V V standard output I O = 4 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V Qn bus driver output I O = 6 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V V OL LOW-level output voltage V I ==V IH or V IL all outputs I O =20µA; V CC = 2.0 V V I O =20µA; V CC = 4.5 V V I O =20µA; V CC = 6.0 V V standard output I O = 4 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V Qn bus driver output I O = 6 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V I LI input leakage current V I =V CC or GND; V CC = 6.0 V - - ±1.0 µa I OZ 3-state output OFF-state current V I =V IH or V IL ; V O =V CC or GND; - - ±10.0 µa V CC = 6.0 V I CC quiescent supply current V I =V CC or GND; I O =0A; V CC = 6.0 V µa Product data sheet Rev March of 25

12 11. Dynamic characteristics Table 8: Dynamic characteristics GND = 0 V; t r =t f = 6 ns; C L = 50 pf; unless otherwise specified; see Figure 14. Symbol Parameter Conditions Min Typ Max Unit T amb = 25 C t PHL, t PLH propagation delay CPC to see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns propagation delay CPR to Qn see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PLH propagation delay MRC to see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PZH, t PZL 3-state output enable time see Figure 11 OE to Qn V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PHZ, t PLZ 3-state output disable time see Figure 11 OE to Qn V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W CPC and CPR clock pulse see Figure 8 and Figure 9 width HIGH or LOW V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns MRC reset pulse width LOW see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time CPC to CPR see Figure 13 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns set-up time CE to CPC see Figure 12 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev March of 25

13 Table 8: Dynamic characteristics continued GND = 0 V; t r =t f = 6 ns; C L = 50 pf; unless otherwise specified; see Figure 14. Symbol Parameter Conditions Min Typ Max Unit t h hold time CE to CPC see Figure 12 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t rem removal time MRC to CPC see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns f max maximum clock pulse see Figure 8 and Figure 9 frequency CPC or CPR V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 6.0 V MHz C PD power dissipation capacitance [1] [2] pf T amb = 40 C to +85 C t PHL, t PLH propagation delay CPC to see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns propagation delay CPR to Qn see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PLH propagation delay MRC to see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PZH, t PZL 3-state output enable time see Figure 11 OE to Qn V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PHZ, t PLZ 3-state output disable time see Figure 11 OE to Qn V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev March of 25

14 Table 8: Dynamic characteristics continued GND = 0 V; t r =t f = 6 ns; C L = 50 pf; unless otherwise specified; see Figure 14. Symbol Parameter Conditions Min Typ Max Unit t W CPC and CPR clock pulse width HIGH or LOW see Figure 8 and Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns MRC reset pulse width LOW see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time CPC to CPR see Figure 13 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns set-up time CE to CPC see Figure 12 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t h hold time CE to CPC see Figure 12 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t rem removal time MRC to CPC see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns f max maximum clock pulse see Figure 8 and Figure 9 frequency CPC or CPR V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 6.0 V MHz Product data sheet Rev March of 25

15 Table 8: Dynamic characteristics continued GND = 0 V; t r =t f = 6 ns; C L = 50 pf; unless otherwise specified; see Figure 14. Symbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +125 C t PHL, t PLH propagation delay CPC to t PLH t PZH, t PZL t PHZ, t PLZ t W propagation delay CPR to Qn propagation delay MRC to 3-state output enable time OE to Qn 3-state output disable time OE to Qn CPC and CPR clock pulse width HIGH or LOW see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns see Figure 11 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns see Figure 11 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns see Figure 8 and Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns MRC reset pulse width LOW see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time CPC to CPR see Figure 13 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns set-up time CE to CPC see Figure 12 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev March of 25

16 Table 8: Dynamic characteristics continued GND = 0 V; t r =t f = 6 ns; C L = 50 pf; unless otherwise specified; see Figure 14. Symbol Parameter Conditions Min Typ Max Unit t h hold time CE to CPC see Figure 12 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t rem removal time MRC to CPC see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns f max maximum clock pulse frequency CPC or CPR see Figure 8 and Figure 9 V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 6.0 V MHz [1] C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i N + (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. [2] The condition is V I = GND to V CC. 12. Waveforms V I 1/f max CPC input output GND V OH V OL t PHL t W t PLH 001aac550 Fig 8. Measurement points: = 0.5 V I. V OL and V OH are the typical output voltage drop that occur with the output load. Waveforms showing the propagation delays from the counter clock input (CPC) to ripple carry () output and the CPC pulse width Product data sheet Rev March of 25

17 1/f max V I CPR input Qn output GND V OH V OL t PLH t W t PHL 001aac549 Fig 9. Measurement points: = 0.5 V I. V OL and V OH are the typical output voltage drop that occur with the output load. Waveforms showing the propagation delays from the register clock input (CPR) to output (Qn) and the register clock pulse width t W V I MRC input GND t PLH V OH output V OL V I t rem CPC input GND 001aac551 Measurement points: = 0.5 V I. V OL and V OH are the typical output voltage drop that occur with the output load. Fig 10. Waveforms showing the propagation delays from the master reset counter input (MRC) to output (), the MRC pulse width and removal time Product data sheet Rev March of 25

18 OE input V I GND V CC output LOW-to-OFF OFF-to-LOW V OL t PLZ 10 % t PZL output V OH HIGH-to-OFF OFF-to-HIGH GND t PHZ outputs enabled 90 % outputs disabled t PZH outputs enabled 001aac554 Measurement points: = 0.5 V I. V OL and V OH are the typical output voltage drop that occur with the output load. Fig 11. Waveforms showing the 3-state enable and disable times V I CE input GND t su t h t su t h V OH CPC input V OL 001aac553 Measurement points: = 0.5 V I. V OL and V OH are the typical output voltage drop that occur with the output load. Fig 12. Waveforms showing the set-up and hold times for the count enable input (CE) to the counter clock input (CPC) V I CPC input GND t su t h V OH CPR input V OL 001aac552 Measurement points: = 0.5 V I. V OL and V OH are the typical output voltage drop that occur with the output load. Fig 13. Waveforms showing the set-up and hold times for the counter clock input (CPC) to the register clock input (CPR) Product data sheet Rev March of 25

19 V CC V CC PULSE GENERATOR V I D.U.T V O R L = 1 kω open R T C L 50 pf mgk563 Test data is given in Table 9. Definitions test circuit: R L = Load resistor. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to output impedance Z o of the pulse generator. Fig 14. Load circuitry for switching times Table 9: Test data Supply voltage Input Load Switch position V CC V I t r, t f C L R L t PLH, t PHL t PZL, t PLZ t PZH, t PHZ 2.0 V to 6.0 V V CC 6 ns 50 pf 1 kω open V CC GND Product data sheet Rev March of 25

20 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y H E v M A Z 16 9 Q A 2 A 1 (A ) 3 A pin 1 index θ L p 1 8 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max A 1 A 2 A 3 b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT E07 MS Fig 15. Package outline SOT109-1 (SO16) Product data sheet Rev March of 25

21 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y H E v M A Z 16 9 pin 1 index A 2 A 1 Q (A ) 3 A θ 1 8 e b p w M L detail X L p mm scale DIMENSIONS (mm are the original dimensions) A UNIT A 1 A 2 A 3 b p c D (1) E (2) e H (1) E L L p Q v w y Z max. mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA SOT403-1 MO-153 EUROPEAN PROJECTION ISSUE DATE Fig 16. Package outline SOT403-1 (TSSOP16) Product data sheet Rev March of 25

22 DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm SOT763-1 D B A E A A1 c terminal 1 index area detail X terminal 1 index area e 1 e b 2 7 v M w M C C A B y 1 C C y L 1 8 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max. A 1 b c D (1) D h E (1) E h e e 1 L v w y y 1 mm Note 1. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA SOT MO EUROPEAN PROJECTION ISSUE DATE Fig 17. Package outline SOT763-1 (DHVQFN16) Product data sheet Rev March of 25

23 14. Revision history Table 10: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes _ Product data sheet Product data sheet Rev March of 25

24 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions 17. Disclaimers Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Life support These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 18. Contact information For additional information, please visit: For sales office addresses, send an to: sales.addresses@ Product data sheet Rev March of 25

25 19. Contents 1 General description Features Quick reference data Ordering information Functional diagram Pinning information Pinning Pin description Functional description Function table Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline Revision history Data sheet status Definitions Disclaimers Contact information Koninklijke Philips Electronics N.V All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 30 March 2005 Document number: Published in The Netherlands