Quick Review. ESE319 Introduction to Microelectronics. and Q1 = Q2, what is the value of V Odm. If R C1 = R C2. s.t. R C1. Let Q1 = Q2 and R C1


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1 Quick Review If R C1 = R C2 and Q1 = Q2, what is the value of V Odm? Let Q1 = Q2 and R C1 R C2 s.t. R C1 > R C2, express R C1 & R C2 in terms R C and ΔR C. If V Odm is the differential output offset voltage, what is V OS? 1
2 Quick Review 0 V OS V OS = V O dm A v dm = V V O dm OS A v dm A v dm =g m R C 2
3 Quick Review Input Referred Offset Voltages Input Offset Current V OS RC =V T V OS I S =V T R C R C I S I S I OS =I B Total Input Referred Offset Voltage V OS rms = V OS RC 2 V OS I S 2 =V T R C R C 2 I S I S 2 3
4 Quick Review  Summary 1. DC offset voltage and current occur due to mismatches in the BJT differential amplifier external resistors and transistor parameters (I s and β). 2. They are imperfections that are inherent to all differential amplifiers and their applications (e.g. op amps). 3. DC offset voltage and current are statistical quantities, i.e. no two differential amplifiers will have the same offset voltage and current. 4. MOS differential amplifiers have zero offset current. 4
5 Differential Amplifier with Active Loads Active load basics PNP BJT current mirror Small signal model Design example and simulation Comparison of CMRR with resistive load design 5
6 Differential Amp Active Loads Basics 1 Vcc Rc1 Vcg2 Vcg1 Rc2 Iref Rref Vcc Q5 Q6 Q7 Rb1 Rb2 Vee + + Vc1 Vc2 Iref1 Rref1 Rref2 Iref2 + Vi1 Q1 Q2 + Vi2 r o = V A I C R C R C2 r o7 R C1 r o6 Q3 Q4 Vee PROBLEM: Op. Pt. V C1, V C2 very sensitive to mismatch I ref1 I ref2. 6
7 Differential Amp Active Loads Basics 2 I C2 I C2, I C7 slope = 1/R C2 V BE2 slope = 1/r o7 V BE2 V CC V CE2 V CC V CE2 7
8 Differential Amp Active Loads Basics 3 V c1 V c2 V V c1 c2 PROBLEM: Op. Pt. V C1, V C2 very sensitive to mismatch I ref1 I ref2. SOLUTION: all currents referenced to I ref1. Op. Pt. sensitivity eliminated. COST: output singleended only. GOOD NEWS: CMRR is much improved over resistiveload differential amp singleended CMRR. 8
9 NOTES A pnp current mirror (source) is an effective active load for an npn CE stage. As we will later see, the collector resistance equals the parallel combination of output resistances of the active load stage and the gain stage BJTs. I source An npn current mirror stage (sink) is also an effective active load for an npn emitterfollower (CC) stage. I sink 9
10 V CC r o3 Q2 Q3 I C3 =I C1 I REF2 V C1 R ref2 I REF1 Q1 R ref1 I C5 =I E1 Q5 Q6 r o5 V EE If I REF1 and I REF2 are different by 4%, the Q1 collector voltage V C1 will change by about 2V. 10
11 Quick Review  PNP BJT I R 1 V B I B R E I E Voltage bias equations: I E = V CC V EB V B R E 0.7 V R 2 R C I C I E = V CC V B 0.7 R E Note reference current directions! V B I R 2 = R 2 R 1 R 2 V CC I I E 10 11
12 Quick Review  PNP BJT R 1 i B R E i E Usual Large signal equations: i C =I S e v EB V T npn i C =I S e v BE V T R 2 R C i C i B = i C i E =i C i B = 1 i C i C = i E 12
13 Quick Review  PNP BJT Quick Review  PNP Small Signal Model i b i c i b i c i e i e 13
14 PNP Mirror Q1 = Q2: g m1 = g m2 = g mp ; r e1 = r e2 = r ep ; r π1 = r π2 = r πp ; β 1 = β 2 = β p g m v eb I Q1 R REF Q2 I r πp g r V CC =V EB1 I R mp v eb op REF I = V CC 0.7 R REF B1 E1 C1 ix Small signal model: B2 r πp E2 g mp v eb C2 r op v EB2 =v EB1 14
15 PNP Mirror Small signal model: E1 ix E2 r πp B1 C1 g mp v eb Current i x into the emitter of Q1: r op B2 r πp g mp v eb C2 r op recall r p = p g mb i x = v eb r p g mp v eb = 1 r p g mp v eb r ep = r p p 1 = i g mp x g p mp v = 1 p eb p g mp v eb v eb r ep 15
16 ESE319 Introduction to Microelectronics Simplified Midband DM Small Signal Model v idm Q1 i e v be2 = v eb1 Q3 I Q4 i e Q2 v c4dm v idm V CC V EE v idm Q3 = Q4 Q1 = Q2 i r v c4dm is singleended output. ocs virtual ground v e = 0, i = 0 NOTE: 1. Due to imbalance created by active load current mirror, only singleended output is available from common collector of Q2 and Q4. 2. Q3, Q4 emitter symmetry creates virtual ground at amplifier emitter connection. B3 r πn B1=C1 r on E1 r ep r op r πp g mp v eb1 r op B2 C2 C3 C4 B4 g mn vdm v idm i e E3 v e E2 E4 i e r on vdm g mn v idm r πn v c4dm 16 v idm
17 Simplified DM Small Signal Model cont. Matched NPN: Q3 = Q4 g m3 =g m4 =g mn r e3 =r e4 =r en r 3 =r 4 =r n r o3 =r o4 =r on combining parallel resistances to ground r ep r op r p r on r ep B3 E1 C3=B1=C1=B2 r πn v idm v idm E3 r ep g mn vdm v idm From previous slide r ep r op r p r on r ep C2 r on E4 g mp v eb1 C4 E2 vdm r πn g mn v idm r op B4 v idm v c4dm r on r ep r op r ocs r p Matched PNP Q1 = Q2 g m1 =g m2 =g mp r e1 =r e2 =r ep v c4dm virtual ground r 1 =r 2 =r p r o1 =r o2 =r op 17
18 Simplified DM Small Signal Model  cont. From previous slide: r ep r op r p r on r ep B3 1 r n B1 E1 r ep vdm Matched NPN: Q3 = Q4 Matched PNP: Q1 = Q2 vdm v idm v idm Matched NPN & PNP transistors have been assumed throughout. 2 g mn v i dm i c2 r on C2 g mp v eb1 C4 i c4 3 E2 r n r op B4 v eb1 g mn v i dm 2 r ep i c2 =g mp v eb1 =g mp g mn where: r ep 1 g mp E3 E4 hence: g mn v i dm virtual ground v c4 dm Determine i c2 and i c4 : by inspection: 1 v i dm 2 r ep i c2 g mn v i dm 2 v i dm i c4 =g mn 2 i c2 i c
19 Simplified DM Small Signal Model  cont. Matched NPN: Q3 = Q4 Matched PNP: Q1 = Q2 Note that the resistors r op (PNP) & r on (NPN) are in parallel, and driven by two nearly equal parallel VCCSs. r ep g mn v i dm v c4 dm R o =r op r on r o r o = r o 2 v i dm v c4 dm = i c2 i c4 R o =2 g mn 2 R o v c4 dm =g mn R o v i dm From previous slide: i c2 g mn v i dm 2 =i c4 g mn v i dm A v dm4 = v c4 dm v i dm =g mn r op r on r op A v cm4 = v c4 cm also = v i cm p r ocs r o = bias current source output resistance 19
20 Quick Review Iref1? Iref1 What is accomplished by the progression differential amplifier circuits from 1. to 2. above? What is accomplished by the progression differential amplifier circuits from 2. to 3. above? Is circuit 3. a perfect replacement for circuit 1.? 20
21 Quick Review r op r on 21
22 Quick Review v eb1 g mn v i dm 2 r ep g mp v eb1 =g mp g mn v i dm 2 r ep =g mn v i dm 2 B1=C1=B2=C3 B3 g mn v idm v eb1 C2=C4 g mp v eb1 i c2 r on r op B4 E1=E3 E2=E4 Next show: A v cm4 = v c4 cm v i cm = v c4 dm = g mp v eb1 g mn v i dm 2 r on r op =g mn v i dm r on r op r op p r ocs A v dm4 = v c4 dm v i dm =g mn r op r on where r ocs = I output resistance 22
23 Simplified Midband CM Small Signal Model Matched NPN: Q3 = Q4 (r en, r πn, g mn, β n ) Matched PNP: Q1 = Q2 (r ep, r πp, g mp, β p ) E1 = E2 i e r ep r p B1=C1 = B2 B3 r n r on v icm v eb1 C3 n i b E3 vcm v e E4 B2 i c4 r on g mp v eb1 C2 C4 B4 n vcm i b i rop =g mp v eb1 i c4 r op v c4cm r n v icm i e i e v i cm = r n 1 i e 2 r ocs i e 2 r ocs i e i e v i cm 2 r ocs v i cm v eb1 =r pi p r ep i e =r p r ep 2 r ocs i = 2i e r ocs i c4 = n i b i e v i cm 2 r ocs. 0 v c4 cm =r op g mp v eb1 i c4 =r op g mp r p r ep 1 v i cm 2 r ocs 23
24 Simplified CM Small Signal Model  cont. r ep r p i c4 g mp v eb1 r op v c4cm r b r ep = r ep r ep 1 p r ep r ep 1 p = r ep 1 p 2 p g mp = p r p = p 1 p 1 r ep v icm r n r on n i b v e r on n i b r n v icm From previous slide ii i e r ocs i e v c4 cm = r op g 2 r mp r p r ep 1 v i cm ocs g mp r p r ep = p 1 r ep 1 p = p 1 p r ep 2 p 2 p A v cm = v c4 cm = r op g v i cm 2 r mp r p r ep 1 = r op p 1 ocs 2 r ocs 2 p.= r op 2 r ocs 2 2 p r op 2 r ocs 2 p r op r op => A v cm4 = 2 p r ocs p r ocs 24
25 I REF DM Diff Amp 2N3906 PNP Active Loads v c2dm Design: set R3 for I REF = 10 ma R3= 23.3V 10 ma =2.33 k A v dm2 = v o dm v i dm =g m r o2 r o8 v idm A vdm2(db) = khz = MHz Matched NPN: Q1 = Q2 = Q3 = Q4 Matched PNP: Q7 = Q8 25
26 CM Diff Amp 2N3906 PNP Active Loads v c2cm A v cm2 = v c2 cm v i cm A vcm2(db) = khz = MHz A vdm2(db) = khz v icm Matched NPN: Q1 = Q2 = Q3 = Q4 Matched PNP: Q7 = Q8 Note: 55 db 20log CMRR=20 log 10 A v dm2 A v cm2.= A v dm2 db A v cm2 db = k Hz 26
27 CMRR Comparison cont. R C 56kΩ 56k Ohm v c2 R56k C Ohm 56kΩ R 2.33k ref Ohm 233kΩ v c2 R E R E 100Ω 100Ω v idm vdm I v idm vdm v idm ref =0.2 ma v v idm icm r o =500 k v icm I ref =10 ma A v dm2 db =20 log 10 R C R E =55 k Hz R A v cm2 db =20log C 10 = khz 2 r o CMRR = 80 1 khz Sanity Check: V Rc = (56 kω) (0.1 ma) = 5.6 V! A vdm2(db) = 55 1 khz A vcm2(db) = khz CMRR = khz 27
28 Summary Active load advantages: 1. Minimizes number of passive elements needed. 2. Can produce very high gain in one stage. 3. Much larger singleended CMRR then singleended CMRR for resistive load differential amplifier. 3. Inherent differentialtosingleended conversion. Active load disadvantages: 1. No differential output available. 28
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