Adding a New Dimension to Physical Design. Sachin Sapatnekar University of Minnesota

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1 Adding a New Dimension to Physical Design Sachin Sapatnekar University of Minnesota 1

2 Outline What is 3D about? Why 3D? 3D-specific challenges 3D analysis and optimization 2

3 Planning a city: Land usage [Somewhere in the American midwest; pop. density typically about 20 persons/km 2 ] [Minneapolis, p.d. = 2,700/km 2 ] [SF= 6,688/km 2 ] [New York=10,600/km 2 ] 3

4 Types of 3D circuits PCB stacking Memory vertical TFTs Wafer stacking [Fraunhofer IZM] [Matrix Semiconductor] [ Example application Antenna Layer Down- conversion layer: IF, ADC, Digital Baseband Digital processing Back- Metal LNA / Mixer Isolation plane 4

5 Example of a commercial application [Beyne, IMEC] 5

6 Example 3D processes [H. Hedler, ISSCC 2007 Qimonda] [Koyanagi, Tohoku U./Zycube] [Hedler, Qimonda] [IBM] 6

7 Through-silicon vias (TSVs) Keep-out distance [Tezzarron] [Nowak, Qualcomm] 7

8 Schematic of a 3D IC Detailed view Generalized view Interlayer Via Layer 5 Inter-layer bonds Layer 4 Layer 3 Layer 2 Metal level of wafer 1 Layer 1 Device level 1 Bulk Substrate ~10µm ~500µm SOI wafers with bulk substrate removed 1µm Bulk wafer Adapted from [Das et al., ISVLSI, 2003] by B. Goplen 8

9 Outline What is 3D about? Why 3D? 3D-specific challenges 3D analysis and optimization 9

10 Another dimension to scaling [Intel] 3D provides an alternative avenue towards increasing system sizes Orthogonal to device scaling 10

11 3D Interconnects Reduced wire lengths 2D DRAM Theoretically 3D For an L L 2D chip, max wire length reduces from 2L to 2L m DRAM DRAM DRAM DRAM L2 Cache Thermal Gradient Net Density (#/mm) D Global Net Distributions 4 Strata 2 Strata 1 Stratum CPU & L1Cache Heat Sink Length (mm) 11

12 Why are shorter wires good? Sequential critical length ( cycle reach ) trends 7 Relative critical seq. length M6 90nm M3 65nm 45nm 32nm 8x wire 4x wire [Intel] Critical interbuffer length also shrinking (i.e., buffer count increasing) P6, ~core cycle reach 65nm, ~5.2 GHz [IBM] 2x wire 1x wire 12

13 Other benefits Improved isolation in 3D Critical for analog/rf ckts Lower digital/mixed-signal noise Shielding is possible either using metal layers, or by leveraging bonding material (Cu) [Das et al., ISPD04] Heterogeneous integration Different layers can be made of different materials Can integrate, for example CMOS GaAs Optical elements (VCSELs) MEMS/NEMS Exotic cooling technologies (micropumps, piezoelectric devices, microrefrigerators) 13

14 Outline What is 3D about? Why 3D? 3D-specific challenges 3D analysis and optimization 14

15 Geometrical challenges Detailed view Generalized view Interlayer Via Inter-layer bonds Metal level of wafer 1 Layer 1 Device level 1 Layer 5 Layer 4 Layer 3 Layer 2 Bulk Substrate 10µm 500µm Adapted from [Das et al., ISVLSI, 2003] by B. Goplen SOI wafers with bulk substrate removed 1µm Bulk wafer 15

16 Thermal challenges Each layer generates heat Heat sink at the end(s) Simple analysis Power(3D)/Power(2D) = m m = # layers Let R sink = thermal resistance of heat sink T = Power R sink m times worse for 3D! And this does not account for Increased effective R sink Leakage power effects, T-leakage feedback Thermal bottleneck: a major problem for 3D Layer 5 Layer 4 Layer 3 Layer 2 Layer 1 Bulk Substrate 16

17 Thermal impact on circuit performance Gate delays change with T Mobility goes down V th goes down Wire delays change with T Leakage increases with T Reliability degrades with T NBTI, electromigration Which effect wins? Positive, negative, mixed T dependency SiH + h + Si + + ½H 2 Si H Si H H 2 Si H Substrate Gate Oxide Poly Can use better heat sinks, but The same circuit at various process corners Heat sink cost vs. Power 17

18 Power delivery challenges Each layer draws current from the power grid Power pins at the extreme end tier(s) Simple analysis Current(3D)/Current(2D) = m m = # layers Let R grid = resistance of power grid V drop = Current R grid m times worse for 3D! And this does not account for Increased effective R grid Leakage power effects, increased current due to T-leakage feedback Power bottleneck: a major problem for 3D Layer 5 Layer 4 Layer 3 Layer 2 Layer 1 Bulk Substrate 18

19 Power supply integrity in 3D Greater challenge in 3D due to via resistance, limited number of supply pins Pins Current per power pin (2D) ITRS The Trend of Current per Power Pin from ITRS 300 2D [Zhan, ICCAD07] 3D Current per Power Pin (ma) Year 19

20 Yield/test challenges Yield due to spot defects reduces exponentially with area Smaller areas imply better yield Stack together smaller die; yield improves! (Note that stacking wafers together does not help!) Problem [Mak, Intel] Need to have known-good die (KGD) Must test die prior to 3D assembly Testing thinned die is hard: mechanically too weak for probe pressure! Can test die prior to thinning but then, connections to other layers are untested! 20

21 Outline What is 3D about? Why 3D? 3D-specific challenges 3D analysis and optimization 21

22 Thermal analysis Heat generation Switching gates/blocks act as heat sources Time constants for heat of the order of ms or more Thermal equation: partial differential equation K x Boundary conditions corresponding to the ambient, heat sink, etc. Self-consistency Power = f(t) T = g(power) x 2 T 2 + K y 2 y T 2 + K z 2 z T 2 + Q(x, y,z) = 0 22

23 Thermal solution techniques Numerical: solve large, sparse systems of linear equations Finite difference method: thermal electrical equivalence System structure is similar to power grids (good!) + ~ heat sources wafer... +~... Current sources power, voltage temperature Finite element method Semi-analytical Green functions (fast, appropriate for early analysis) z ambient temperature y x 23

24 Thermal optimization Minimize power usage P cells Rearrange heat sources R chip Improved thermal conduits Chip Improved heat sinking R heat sink Heat Sink 24

25 3D floorplanning [Zhou, ICCAD07] 25

26 3D placement Incorporate thermal issues Force-directed vs. partitioning methods IOPad 1 Net1 Cell 1 Cell 2 Cell 3 TRR Net 1 TRR Net 3 TRR Net 2 Net2 Net3 Cell 5 Cell 4 TRR Net 4 TRR Net 5 IOPad 2 Heat Sink 26

27 Interlayer via count vs. wirelength (ibm01) layers Interlayer Vias per Interlayer layers 3 layers 4 layers 5 layers 10 layers 9 layers 8 layers 7 layers 6 layers 5 layers 4 layers 3 layers Wirelength, m 1 layer 27

28 Thermal vias Thermal Via Substrate Thermal vias Electrically isolated vias Used for heat conduction Thermal via regions Thermal Via Region Contains thermal vias Predictable obstacle for routing Variable density of thermal vias z y x Row Region Inter-Row Region } Inter-layer } Layer } Bulk Substrate 28

29 Temperature profile Before Thermal Via Placement After Thermal Via Placement 29

30 Thermal via insertion Temperature Profile Thermal Via Regions 30

31 3D routing with integrated thermal via insertion Build good heat conduction path through dielectric: Thermal vias: interlayers vias dedicated to thermal conduction. Thermal wires: metal wires improves lateral heat conduction. Thermal vias + thermal wires a thermal conduction network. thermal vias thermal wires Thermal wires compete with lateral signal wire routing. Thermal vias: large, can block lateral signal routing capacity. [Zhang, ASPDAC06] 31

32 Active cooling techniques Polymer cover TWV Si Si microchannel heat sink Si Die Trimodal I/O Fluidic I/O Electrical I/O Optical I/O Optical I/O Fluidic I/O [Bakir, GaTech - CICC 07] 32

33 Microfluidic cooling Si Die TSV-E TSV-F Trimodal I/Os Cu wire Optical waveguide Fluidic channel Temperature rise on heaters (C) Flow rate = 34 ml/min Flow rate = 78 ml/min Flow rate = 104 ml/min Flow rate = 125 ml/min Area: 8 mm Localized power density (W/cm2) [Bakir, GaTech] 33

34 3D and multicore systems NoCs 3D bus/noc hybrid [Karnik, Intel] [Xie, Penn State] 34

35 3D NoCs Need to build custom NoCs for 3D architectures Floorplanning + NoC design 20 0 v v Bandwidth in MB/s v 5 3D-specific challenges Technology constraints, like TSV# Tier assignment Placement of switches Accurate power and delay modeling v s 2 v 1 v 2 Core graph v 5 tier 1 tier 0 s 1 v 2 v 4 v 3 s 3 3D custom NoC architecture [Zhou, ASPDAC10] 35

36 Conclusion Numerous challenging problems in 3D IC design Significant research already in floorplanning, placement, routing New challenges in architectural-level issues, NoCs, power delivery, test 36

37 Questions? Any You! Thank 37

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