Lecture 12: Energy and Power. James C. Hoe Department of ECE Carnegie Mellon University
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1 Lecture 12: Energy and Power James C. Hoe Department of ECE Carnegie Mellon University S18 L12 S1, James C. Hoe, CMU/ECE/CALCM, 2018
2 Housekeeping Your goal today a working understanding of energy and power appreciate their significance in comp arch today Notices Lab 2, due this week HW 3, due next Wednesday Handout #10: Lab 3, due the week of 3/26 Readings Design challenges of technology scaling, Borkar, Synthesis Lectures (advanced optional): Comp Arch Techniques for Power Efficiency, 2008 Power Efficient Comp Arch: Recent Advances, S18 L12 S2, James C. Hoe, CMU/ECE/CALCM, 2018
3 Energy and Power CMOS logic transitions involve charging and discharging of parasitic capacitances Energy (Joule) dissipated as resistive heat when charges flow from VDD to GND takes a certain amount of energy per operation (e.g., addition, reg read/write, (dis)charge a node) to the first order, energy amount of compute Power (Watt=Joule/s) is rate of energy dissipation more op/sec then more Joules/sec to the first order, power performance S18 L12 S3, James C. Hoe, CMU/ECE/CALCM, 2018
4 Make sure we agree what is what Electric bill is for energy (kilowatt hour) not power Bigger phone battery holds more energy Faster charger refills battery s energy in a shorter time, hence, higher power Chargers rated for max power not max energy For a given amount of energy (say a fully charged battery), lower power device runs longer For a given device, bigger battery lasts longer World energy consumption > Joule in 1 year A nuclear generator generates ~ 10 9 Joule in 1 sec S18 L12 S4, James C. Hoe, CMU/ECE/CALCM, 2018
5 S18 L12 S5, James C. Hoe, CMU/ECE/CALCM, 2018 Some nitty gritty
6 Work Work and Runtime scalar quantity for amount of work associated with a task e.g., number of instructions to compute a SHA256 hash T = Work / k perf runtime to perform a task k perf is a scalar constant for the rate in which work is performed, e.g., instructions per second S18 L12 S6, James C. Hoe, CMU/ECE/CALCM, 2018
7 E switch = k switch Work S18 L12 S7, James C. Hoe, CMU/ECE/CALCM, 2018 Energy and Power switching energy associated with task k switch is a scalar constant for energy per unit work E static = k static T = k static Work / k perf leakage energy just to keep the chip powered on k static is the so called leakage power Faster execution means lower leakage energy??? E total = E switch +E static = k switch Work + k static Work/k perf P total = E total /T = k switch k perf + k static Static power can be 50% in high perf processors
8 In Short T = Work / k perf less work finishes faster E = E switch + E static = (k switch + k static /k perf ) Work less work use less energy P = P switch + P static = k switch k perf + k static power independent of amount of work Reality check Work not a simple scalar, inst mix, dependencies... k s are neither scalar nor constant k perf : inst/sec k switch : J/inst k static : J/sec S18 L12 S8, James C. Hoe, CMU/ECE/CALCM, 2018
9 k switch, k static, k perf not independent k switch k perf + k static Power Perf > 1 More complicated arch increases kswitch Faster transistors increases k static S18 L12 S9, James C. Hoe, CMU/ECE/CALCM, 2018 k perf
10 S18 L12 S10, James C. Hoe, CMU/ECE/CALCM, 2018 Why so important now?
11 Technology Scaling for Dummies Planned scaling occurs in discrete nodes where each is ~0.7x of the previous in linear dimension Take the same design, reducing linear dimensions by 0.7x (aka gate shrink ) leads to **ideally** die area = 0.5x delay = 0.7x; frequency=1.43x capacitance = 0.7x Vdd = 0.7x (constant field) or 1x (constant voltage) power = 0.5x (const. field) or 1x (const. voltage) Take the same area, then transistor count = 2x power = 1x (const field) or 2x (const voltage) S18 L12 S11, James C. Hoe, CMU/ECE/CALCM, 2018
12 S18 L12 S12, James C. Hoe, CMU/ECE/CALCM, 2018 The Other Moore s Law
13 Moore s Law Performance According to scaling complexity: 1x transistors at 1.43x frequency 1.43x performance at 0.5x complexity: 2x transistors at 1.43x frequency 2.8x performance at constant power Historically though, for high perf CPUs ~2x transistors ~2x frequency (note: faster than scaling predicts) all together, ~2x performance at ~2x power S18 L12 S13, James C. Hoe, CMU/ECE/CALCM, 2018 Why?
14 Performance (In)efficiency To hit expected performance target push frequency harder by deepening pipelines used the 2x transistors to build more complicated microarchitectures so fast/deep pipelines don t stall (i.e., caches, BP, superscalar, out of order) The consequence of performance inefficiency is limit of economical cooling [ITRS] 2005, Intel P4 Tehas 150W [Borkar, IEEE Micro, July 1999] S18 L12 S14, James C. Hoe, CMU/ECE/CALCM, 2018
15 Moore s Law without Dennard Scaling Intl. Technology Roadmap for Semiconductors logic density VDD >16x 1 25% 0 node label ?? S18 L12 S15, James C. Hoe, CMU/ECE/CALCM, 2018 Under fixed power ceiling, more ops/second only achievable if less Joules/op?
16 Frequency and Voltage Scaling: run slower at lower energy per op S18 L12 S16, James C. Hoe, CMU/ECE/CALCM, 2018
17 Frequency and Voltage Scaling Switching energy per transition is ½CV 2 (modeling parasitic capacitance) Switching power at f transitions per sec is ½CV 2 f To reduce power, slow down the clock If clock is slower (f ), reduce supply voltage (V ) too since transistors don t need to be as fast reduced switching energy, ½CV 2 ½CV 2 lower V also reduced leakage current/power S18 L12 S17, James C. Hoe, CMU/ECE/CALCM, 2018
18 Frequency Scaling (by itself) IfWork / k perf < T bound, we can derate performance by frequency scaling by a factor s freq (Work/k perf )/T bound < s freq <1 s.t. k perf =k perf s freq T = Work / (k perf s freq ) 1/s freq longer runtime E = (k switch + k static / (k perf s freq )) Work higher (leakage) energy due to longer runtime P = k switch k perf s freq + k static lower (switching) power due to longer runtime S18 L12 S18, James C. Hoe, CMU/ECE/CALCM, 2018 Not such a good idea
19 Intel P4 660 Frequency Scaling: FFT 64K GHz GHz runtime (ms) GHz frequency (MHz) runtime (ms) GHz cycle time (ns) S18 L12 S19, James C. Hoe, CMU/ECE/CALCM, 2018 circa 2005, 90nm
20 Intel P4 660 Frequency Scaling: FFT 64K 100 leakage power power (Watt) measured modeled switching power frequency (MHz) k perf =145 FFT64K/sec; k switching =0.24 J/FFT64K; k static =49.4J/sec S18 L12 S20, James C. Hoe, CMU/ECE/CALCM, 2018
21 Intel P4 660 Frequency Scaling: FFT 64K energy (mjoule) frequency (MHz) measured modeled more energy per fft to run slower!! k perf =145 FFT64K/sec; k switching =0.24 J/FFT64K; k static =49.4J/sec S18 L12 S21, James C. Hoe, CMU/ECE/CALCM, 2018
22 Frequency + Voltage Scaling Frequency scaling by s freq allows supply voltage to be scaled by a corresponding factor s voltage E V 2 thus k switch =k switch s voltage 2 k static =k static s voltage 2~3 very gross approximation T = Work / (k perf s freq ) 1/s freq longer runtime E = (k switch s voltage2 + k static s voltage3 /k perf s freq ) Work P = k switch s voltage2 k perf s freq + k static s 3 voltage superlinear reduction in power and energy to performance degradation S18 L12 S22, James C. Hoe, CMU/ECE/CALCM, 2018
23 Intel P4 660 F+V Scaling: FFT 64K power (Watt) S18 L12 S23, James C. Hoe, CMU/ECE/CALCM, model freq. scaling only 30 model freq&volt scaling, x^2 20 model freq&volt scaling, fitted 10 model freq&volt scaling, x^ frequency (MHz) circa 2005, 90nm
24 Intel P4 660 F+V Scaling: FFT 64K 3500 energy (mjoule) model freq. scaling only model freq&volt scaling, x^2 model freq&volt scaling, fitted model freq&volt scaling, x^ S18 L12 S24, James C. Hoe, CMU/ECE/CALCM, frequency (MHz) circa 2005, 90nm
25 Parallelization: run faster at lower energy per op S18 L12 S25, James C. Hoe, CMU/ECE/CALCM, 2018
26 Cost of Performance in Power technology normalized power (Watt) Better to replace 1 of this by 2 of these; Or N of these Pentium 4 Power Perf [Energy per Instruction Trends in Intel Microprocessors, Grochowski et al., 2006] S18 L12 S26, James C. Hoe, CMU/ECE/CALCM, 2018 technology normalized performance (op/sec)
27 Parallelization Ideal parallelization over N CPUs T = Work / (k perf N) E = (k switch + k static / k perf ) Work N times static power, but N times faster runtime P = N (k switch k perf + k static ) Alternatively, forfeit speedup for power and energy reduction by s freq =1/N (assume s voltage s freq below) T = Work /k perf E = (k switch / N 2 + k static / (k perf N)) Work P = k switch k perf / N 2 + k static / N Also works with using N slower simpler CPUs S18 L12 S27, James C. Hoe, CMU/ECE/CALCM, 2018
28 So what is the problem? Easy to pack more s on a die to stay on Moore s law for aggregate or throughput performance How to use them? life is good if your N units of work is N independent programs just run them what if your N units of work is N operations of the same program? rewrite as parallel program what if your N units of work is N sequentially dependent operations of the same program??? How many s can you use up meaningfully? S18 L12 S28, James C. Hoe, CMU/ECE/CALCM, 2018
29 Moore s Law Scaling with Cores Big Core 1970~ ~?? S18 L12 S29, James C. Hoe, CMU/ECE/CALCM, 2018
30 Remember: it is all about Perf/Watt and Ops/Joules Big Core What will you choose to put on it? GPGPU Custom Logic FPGA S18 L12 S30, James C. Hoe, CMU/ECE/CALCM, 2018 We talk about HW specialization in a later lecture
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