τ gd =Q/I=(CV)/I I d,sat =(µc OX /2)(W/L)(V gs -V TH ) 2 ESE534 Computer Organization Today At Issue Preclass 1 Energy and Delay Tradeoff

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1 ESE534 Computer Organization Today Day 8: February 10, 2010 Energy, Power, Reliability Energy Tradeoffs? Voltage limits and leakage? Variations Transients Thermodynamics meets Information Theory (brief, if we get to it) 1 2 At Issue Many now argue power will be the ultimate scaling limit (not lithography, costs, ) Proliferation of portable and handheld devices battery size and life biggest issues Cooling, energy costs may dominate cost of electronics Even server room applications 3 1GHz case Voltage? Preclass 1 Energy per Operation? Power required for 2 processors? 2GHz case Voltage? Energy per Operation? Power required for 1 processor? 4 Energy and Delay Tradeoff τ gd =Q/I=(CV)/I I d,sat =(µc OX /2)(W/L)(V gs -V TH ) 2 5 E V 2 τ gd 1/V We can trade speed for energy E (τ gd ) 2 constant Τ gd =(CV)/I I d,sat (V gs -V TH ) 2 Martin et al. Power-Aware Computing, Kluwer

2 Parallelism We have Area-Time tradeoffs Compensate slowdown with additional parallelism Question How far can this go? What limits us? trade Area for Energy Architectural Option 7 8 Origin of Power Challenge Challenge: Power Limited capacity to remove heat ~100W/cm 2 force air 1-10W/cm 2 ambient Transistors per chip grow at Moore s Law rate = (1/F) 2 Energy/transistor must decrease at this rate to keep constant power density E/tr CV 2 but V scaling more slowly than F 9 10 Energy per Operation ITRS Vdd Scaling: V Scaling more slowly than F C total = # transistors C tr C tr scales (down) as F # transistors scales as F -2 ok if V scales as F

3 CV 2 scaling from ITRS: More slowly than (1/F) 2 Origin of Power Challenge Transistors per chip grow at Moore s Law rate = (1/F) 2 Energy/tr must decrease at this rate to keep constant E/tr CV 2 f Historical Power Scaling Impact Can already place more transistors on a chip than we can afford to turn on. Power potential challenge/limiter for all future chips. [Horowitz et al. / IEDM 2005] Impact Power Limits Integration Density Limit How far can we reduce voltage? Constant Power Limit 45nm 32nm 22nm 16nm 11nm 17 Source: Carter/Intel

4 Limits MOSFET Conduction Ability to turn off the transistor Noise Parameter Variations 19 From: 20 Transistor Conduction Saturation Region Three regions Subthreshold (V gs <V TH ) Linear (V gs >V TH ) and (V ds < (V gs -V TH )) Saturation (V gs >V TH ) and (V ds > (V gs -V TH )) Saturation Region (V gs >V TH ) (V ds > (V gs -V TH )) I d,sat =(µc OX /2)(W/L)(V gs -V TH ) Linear Region Subthreshold Region (V gs >V TH ) (V ds < (V gs -V TH )) (V gs <V TH ) (( I sub 10 V gs V TH ) / S) I d,lin =(µc OX )(W/L)(V gs -V TH )V ds -(V ds ) 2 /2 23 [Frank, IBM J. R&D v46n2/3p235] 24 4

5 Operating a Transistor Leakage Concerned about I on and I off I on drive current for charging Determines speed: T gd = CV/I I off leakage current Determines leakage power E leak = V I leak T cycle To avoid leakage want I off very small Switch V from 0 to V dd V gs in off state is 0 V gs <V TH (( I sub 10 V gs V TH ) / S) I off (( ) / S) 10 V TH Leakage How maximize I on /I off? I off 10 (( V TH ) / S) S 90mV for single gate S 70mV for double gate 4 orders of magnitude I VT /I off V TH >280mV Leakage limits V TH in turn limits V dd 27 Maximize I on /I off for given V dd? E sw CV 2 Get to pick V TH, V dd I d,sat =(µc OX /2)(W/L)(V gs -V TH ) 2 I d,lin =(µc OX )(W/L)(V gs -V TH )V ds -(V ds ) 2 /2 (( I sub 10 V gs V TH ) / S) 28 E = E sw + E leak E leak = V I leak T cycle E sw CV 2 Preclass 2 (( I sub 10 V gs V TH ) / S) E leak (V)? T cycle (V)? Preclass 2 I chip-leak = N devices I tr-leak

6 In Class Values Assign calculations Collect results V T(v) Esw(V) Eleak(V) E(V) E E E E E E E E E E E E E E E E E E E E-07 4E E E E E E E E E E E E E E E E E E E E E Graph for In Class Impact Subthreshold slope prevents us from scaling voltage down arbitrarily. Induces a minimum operating energy Challenge: Variation Statistical Dopant Count and Placement (This section was a little rushed) 35 Penn ESE535 Spring DeHon 36 [Bernstein et al, IBM JRD 2006] 6

7 V th 65nm Variation Fewer dopants, atoms increasing Variation How do we deal with variation? % variation in V TH (From ITRS prediction) Penn ESE535 Spring DeHon [Bernstein et al, IBM JRD 2006] 38 Impact of Variation? Higher V TH? Not drive as strongly I d,sat (V gs -V TH ) 2 Variation Margin for expected variation Must assume V TH can be any value in range I on,min =I on ( Vth,max ) I d,sat (V gs -V TH ) 2 Lower V TH? Not turn off as well leaks more I off 10 (( V TH ) / S) 39 Probability Distribution V TH Penn ESE535 Spring DeHon 40 Margining Must raise V dd to accommodate worstcase value increase energy I on,min =I on ( Vth,max ) I d,sat (V gs -V TH ) 2 Variation Increasing variation forces higher voltages On top of our leakage limits Probability Distribution V TH Penn ESE535 Spring DeHon

8 Variations Margins growing due to increasing variation Margined value may be worse than older technology? Probability Distribution Delay New Old End of Energy Scaling? Black nominal Grey with variation 43 [Bol et al., IEEE TR VLSI Sys 17(10): ] 44 Chips Growing Larger chips sample further out on distribution curve Lecture Ended Here (Didn t really cover material in transient and thermodynamics sections) From: Transient Sources Challenge Transients Effects Thermal noise Timing Ionizing particles α particle 10 5 to 10 6 electrons Calculated gates with electrons last time Even if CMOS restores, takes time

9 Voltage and Error Rate Errors versus Frequency V CC & Temperature F CLK Guardband Conventional Design Max TP Resilient Design Max TP 49 [Austin et al.--ieee Computer, March 2004] [Bowman, ISSCC 2008] 50 Scaling and Error Rates Power and Reliability SEU/bit Norm to 130nm 10 1 Increasing Error Rates 2X bit/latch count increase per generation Technology (nm) logic cache arrays Intersection is the challenge Push V dd in opposite directions Both reach inflection points From doesn t matter To major concern Source: Carter/Intel Lower Bound? Thermodynamics Reducing entropy costs energy Single bit gate output Set from previous value to 0 or 1 Reduce state space by factor of 2 Entropy: ΔS= k ln(before/after)=k ln2 Energy=T ΔS=kT ln(2) Naively: setting a bit costs at least kt ln(2)

10 Numbers (ITRS 2005) kt ln(2) = J (at R.T. K=300) W/L=3 W=21nm=0.021µm Table 41d C F F E op =CV 2 = F 55 Recycling Thermodynamics only says we have to dissipate energy if we discard information Can we compute without discarding information? Will that help us? 56 Three Reversible Primitives Universal Primitives These primitives Are universal Are all reversible If keep all the intermediates they produce Discard no information Can run computation in reverse Thermodynamics Admin In theory, at least, thermodynamics does not demand that we dissipate any energy (power) in order to compute. Assignment grades, feedback on blackboard for HW1 and HW2 Class Wed. No class next Monday (2/22)

11 Big Ideas Can trade time for energy area for energy Noise and leakage limit voltage scaling Power major limiter going forward Can put more transistors on a chip than can switch Continued scaling demands Deal with noisier components High variation and high transient upsets Thermodynamically admissible to compute without dissipating energy 61 11