Timing analysis and predictability of architectures

Transcription

1 Timing analysis and predictability of architectures Cache analysis Claire Maiza Verimag/INP 01/12/2010 Claire Maiza Synchron /12/ / 18

2 Timing Analysis Frequency Analysis-guaranteed timing bounds Overest. LB BCET WCET UB Exec-time Claire Maiza Synchron /12/ / 18

3 Static Timing Analysis Input Executable Legend: Data Phase CFG Reconstruction Controlflow Graph Value Analysis Loop Bound Analysis Controlflow Analysis Annotated CFG Microarchitectural Analysis Basic Block Timing Info Path Analysis Claire Maiza Synchron /12/ / 18

4 Timing anomalies When local worst-case does not lead to the global worst-case C ready Resource 1 Resource 2 A C D B E Branch Condition Evaluated Cache Hit A Prefetch B - Miss C Resource 1 A D E Resource 2 B C Cache Miss A C Scheduling anomaly. Speculation anomaly. Claire Maiza Synchron /12/ / 18

5 Classification of architectures Timing compositional No timing anomalies e. g., ARM7 Compositional with bounded effects Timing anomalies but no domino effects e. g., TriCore (probably) Non-compositional architectures Timing anomalies, domino effects e. g., PPC 755 from Wilhelm et al.: Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-critical Embedded Systems, IEEE TCAD, July 2009 Claire Maiza Synchron /12/ / 18

6 Why LRU is predictable? LRU (Least Recently Used) forgets about past quickly:???? a a??? b b a?? c c b a? d d c b a FIFO (First In First Out):? a b c a? a b c b? a b c c? a b c d d? a b Claire Maiza Synchron /12/ / 18

7 Preemption does not come for free! The preempting task disturbs the state of performance-enhancing features like caches and pipelines. Once the preempted task resumes its execution, the disturbance may cause additional cache misses. The additional execution time due to additional cache misses is known as the cache-related preemption delay. T 1 T 2 = CRPD = Task Activation Claire Maiza Synchron /12/ / 18

8 How to take preemption cost into account? Where to account for preemption cost? Integrate into WCET Analysis: [Schneider, 2000] assume cache misses everywhere very pessimistic but easy to use in schedulability analysis WCET Analysis + CRPD Analysis: [Lee et al., 1996] WCETbound + n CRPD bound execution time of task with up to n preemptions more precise but only supported by very few schedulability analyses Claire Maiza Synchron /12/ / 18

9 CRPD Analyses Preempted Task: How many useful memory blocks are in the cache? Preempting Task: How much damage can the preempting task do to the cache contents of any task? Preempted + Preempting Task How much damage can the preempting task do to the useful cache contents of the preempted task? Claire Maiza Synchron /12/ / 18

10 Useful Cache Block Analysis What may be cached? Forward May-Analysis! Program point P What may be reused? Backward May-Analysis! minimal distance associativity? Minimal distance to reuse Useful = may be cached and may be reused Claire Maiza Synchron /12/ / 18

11 Useful Cache Block Analysis Combination of two LRU-may-analyses: What may be cached? Forward May-Analysis! What may be reused? Backward May-Analysis! P Minimal age Minimal distance to reuse Minimal age + Minimal distance to reuse associativity = Memory block may be useful Claire Maiza Synchron /12/ / 18

12 Improvement: Path Analysis Some blocks are never useful at the same time: associativity P y associativity y Literature: [Tomiyama and Dutt, 2000, Negi et al., 2003, Staschulat et al., 2007] Claire Maiza Synchron /12/ / 18

13 Analysis of Preempted and Preempting Task: Deeper Combination [Altmeyer et al., 2010] Definition (Resilience) The resilience res P (m) of memory block m at program point P is the greatest l, such that all possible next accesses to m, a) that would be hits without preemption, b) would still be hits in case of a preemption with l accesses at P. Claire Maiza Synchron /12/ / 18

14 Analysis of Preempted and Preempting Task: Deeper Combination [Altmeyer et al., 2010] Definition (Resilience) The resilience res P (m) of memory block m at program point P is the greatest l, such that all possible next accesses to m, a) that would be hits without preemption, b) would still be hits in case of a preemption with l accesses at P. m is useful res(m) = 4 preempted task m a 1 a 2 [m, _, _, _, _, _, _, _] preempting task {e 1, e 2, e 3, e 4 } a 3 m [a 3, e 4, e 3, e 2, e 1, a 2, a 1, m] [m, a 3, e 4, e 3, e 2, e 1, a 2, a 1 ] Claire Maiza Synchron /12/ / 18

15 Do existing approaches work for FIFO, PLRU, etc.? Plain answer: No! Claire Maiza Synchron /12/ / 18

16 Do existing approaches work for FIFO, PLRU, etc.? Plain answer: No! Counterexample for FIFO [Burguière et al., 2009]: ECBs = {x} [b, a] a [b, a] e [e, b] b [e, b] c [c, e] e [c, e] [x, b] a [a, x] e [e, a] b [b, e] c [c, b] e [e, c] 2 useful cache blocks 1 block loaded by the preempting task associativity = 2 But: number of additional misses= 3 2 misses 5 misses Same result for PLRU. Claire Maiza Synchron /12/ / 18

17 Idea [Burguière et al., 2009]: Use Relative Competitiveness Results Some relative competitiveness results: PLRU(n) is (1, 0)-miss-competitive relative to LRU(1 + log 2 n). FIFO(n) is ( n n r+1, r)-miss-competitive relative to LRU(r). = Performing WCET and CRPD analyses assuming LRU(1 + log 2 n) replacement should give correct bounds for PLRU(n). Can we also make use of non-(1, 0)-competitiveness? Claire Maiza Synchron /12/ / 18

18 Applying Relative Competitiveness: A sequence of memory accesses Notation: m = number of misses m = number of misses in the case of preemption m pre = 4 m post = 2 m pre = m pre = 4 m post = m post + m CRPD = 5 Claire Maiza Synchron /12/ / 18

19 Applying Relative Competitiveness: A sequence of memory accesses Notation: m = number of misses m = number of misses in the case of preemption m pre = 4 m post = 2 m pre = m pre = 4 m post = m post + m CRPD = 5 Assume P(t) is (k, c)-miss-competitive rel. to LRU(s). Then: m P(t) = m P(t) pre + m P(t) post Claire Maiza Synchron /12/ / 18

20 Applying Relative Competitiveness: A sequence of memory accesses Notation: m = number of misses m = number of misses in the case of preemption m pre = 4 m post = 2 m pre = m pre = 4 m post = m post + m CRPD = 5 Assume P(t) is (k, c)-miss-competitive rel. to LRU(s). Then: m P(t) = m P(t) pre + m P(t) post [k m LRU(s) pre + c] + [k (m LRU(s) post + m LRU(s) CRPD ) + c] Claire Maiza Synchron /12/ / 18

21 Applying Relative Competitiveness: A sequence of memory accesses Notation: m = number of misses m = number of misses in the case of preemption m pre = 4 m post = 2 m pre = m pre = 4 m post = m post + m CRPD = 5 Assume P(t) is (k, c)-miss-competitive rel. to LRU(s). Then: m P(t) = m P(t) pre + m P(t) post [k m LRU(s) pre + c] + [k (m LRU(s) post = [k m LRU(s) + c] + [k m LRU(s) CRPD + c] + m LRU(s) CRPD ) + c] Claire Maiza Synchron /12/ / 18

22 Applying Relative Competitiveness Assume P(t) is (k, c)-miss-competitive rel. to LRU(s). Then: m P(t) [k m LRU(s) + c] + [k m LRU(s) CRPD + c] In WCET analysis: Take into account k m LRU(s) + c misses In CRPD analysis: Take into account k m LRU(s) CRPD + c misses Claire Maiza Synchron /12/ / 18

23 Summary CRPD bounded using a number of reloads: a miss is the worst-case the reload cost is bounded For LRU, the CRPD can be bounded by analyzing the preempted task: useful cache block analysis the preempting task both, the preempted and the preempting task Resilience Analysis Approaches do not carry over to FIFO, PLRU, etc. immediately First approach: relative competitiveness Claire Maiza Synchron /12/ / 18

24 Altmeyer, S., Burguière, C., and Wilhelm, R. (2009). Computing the maximum blocking time for scheduling with deferred preemption. In Workshop on Software Technologies for Future Dependable Distributed Systems. Altmeyer, S., Maiza, C., and Reineke, J. (2010). Resilience analysis: Tightening the crpd bound for set-associative caches. In LCTES 10: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems, pages , New York, NY, USA. ACM. Burguière, C., Reineke, J., and Altmeyer, S. (2009). Cache-related preemption delay computation for set-associative caches pitfalls and solutions. In Proceedings of 9th International Workshop on Worst-Case Execution Time (WCET) Analysis. Chiou, D. T. (1999). Claire Maiza Synchron /12/ / 18

25 Extending the reach of microprocessors: column and curious caching. PhD thesis. Supervisor-Arvind, and Supervisor-Rudolph, Larry. Kirk, D. B. and Strosnider, J. K. (1990). Smart (strategic memory allocation for real-time) cache design using the mips r3000. In IEEE Real-Time Systems Symposium, pages Lee, C.-G., Hahn, J., Min, S. L., Ha, R., Hong, S., Park, C. Y., Lee, M., and Kim, C. S. (1996). Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. In Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS 96), page 264, Washington, DC, USA. IEEE Computer Society. Lee, S., Lee, C.-G., Lee, M., Min, S. L., and Kim, C.-S. (1998). Claire Maiza Synchron /12/ / 18

26 Limited preemptible scheduling to embrace cache memory in real-time systems. In LCTES 98: Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, pages 51 64, London, UK. Springer-Verlag. Mueller, F. (1995). Compiler support for software-based cache partitioning. SIGPLAN Not., 30(11): Negi, H. S., Mitra, T., and Roychoudhury, A. (2003). Accurate estimation of cache-related preemption delay. In Proceedings of the 1st ACM international conference on Hardware/software codesign and system synthesis (CODES+ISSS 03), pages , New York, NY, USA. ACM. Schneider, J. (2000). Cache and pipeline sensitive fixed priority scheduling for preemptive real-time systems. Claire Maiza Synchron /12/ / 18

27 In In Proceedings of the 21st IEEE Real-Time Systems Symposium (RTSS 2000), pages Staschulat, J. et al. (2007). Scalable precision cache analysis for real-time software. Trans. on Embedded Computing Sys., 6(4):25. Tomiyama, H. and Dutt, N. D. (2000). Program path analysis to bound cache-related preemption delay in preemptive real-time systems. In Proceedings of the 8th ACM international workshop on Hardware/software codesign (CODES 00), pages 67 71, New York, NY, USA. ACM. Wolfe, A. (1994). Software-based cache partitioning for real-time applications. J. Comput. Softw. Eng., 2(3): Claire Maiza Synchron /12/ / 18

28 Deferred Preemption - simplifying the problem Restrict preemptions to a set of predefined preemption points. Introduces new problem: blocking time, time until next preemption point is reached. T 1 BT BT T 2 Context Switch Costs Task Activation Preemption Point Where to place preemptions points, s.t. CRPD is minimized, and Maximum Blocking Time is minimized. Analysis to determine maximum blocking time for given set of preemption points: [Lee et al., 1998, Altmeyer et al., 2009] Claire Maiza Synchron /12/ / 18

29 as dynamic behavior is still present within the individual partitions. Cache Partitioning - eliminating the problem Additional cache misses are due to interference on the cache. P 1 P 2 P 1 = Cache Partitioning eliminates this interference. P 2 set way cache set way cache... Software-based Cache Partitioning [Wolfe, 1994, Mueller, 1995]: Change 2^k layout of instructions and 2^k data such that tasks map to disjoint cache sets Particularly (a) Way-based difficult partitioning for large arrays (b) Set-based partitioning Figure 2.1: Way-based and set-based cache partitioning Partition cache by cache sets and/or cache ways Increases hardware cost There are two schemes in which cache partitioning can be performed. Way-based partitioning [27] allocates a number of ways (columns) to each task (Figure 2.1a). As Renewed interest in multi-cores with shared caches the... Hardware-based Cache Partitioning [Kirk and Strosnider, 1990, Chiou, 1999]: Claire Maiza Synchron /12/ / 18

30 CRPD for PLRU: Pitfalls 1 d 0 b 1 c 0 b 1 a 1 d misses ECBs = {x, y} a b c d a b c d a b c d 1 d* 0 b* 1 a b c d c* 0 a b c d a b c d a b c d b 1 a* 0 d* misses a y c x a y d x b y d x b y d c b y d c b y a c b d a c UCB(s) = 4 ECB(s) = 2 n = 4 But: number of additional misses= 5 Claire Maiza Synchron /12/ / 18

31 Resilience - Domain of the analysis D : D ca D ua (1) with and D ca : M {0,..., k 1} (2) D ua : M {0,..., k 1, } (3) Claire Maiza Synchron /12/ / 18

32 Resilience - Transfer functions t ua : D ua M D ua t ua (ua, m) := 0 m = m λm ua(m. ) ua(m ) ua(m) ua(m ) + 1 ua(m ) < ua(m) ua(m ) < k 1 otherwise (4) t ca : D ca D ua 2 M M D ca t ca (ca, ua, UCB, m) := 0 m = m m / UCB λm. ca(m ) ca(m ) ua(m) ca(m ) = k 1 ca(m ) + 1 ca(m ) < ua(m) (5) Claire Maiza Synchron /12/ / 18