Chapter 9 Computer Design Basics

Transcription

1 Logic ad Computer Desig Fudametals Chapter 9 Computer Desig Basics Part 1 Datapaths

2 Overview Part 1 Datapaths Itroductio Datapath Example Arithmetic Logic Uit (ALU) Shifter Datapath Represetatio Cotrol Word Part 2 A Simple Computer Istructio Set Architecture (ISA) Sigle-Cycle Hardwired Cotrol Istructio Decoder Sample Istructios Sigle Cycle Computer Issues 2

3 Itroductio Computer Specificatio Istructio Set Architecture (ISA) - the specificatio of a computer's appearace to a programmer at its lowest level. Computer Architecture - a high-level descriptio of the hardware implemetig the computer derived from the ISA + additioal specificatios such as speed, cost, ad reliability. 3

4 Itroductio (cotiued) Simple computer architecture decomposed ito: Datapath for performig operatios. Cotrol uit for cotrollig datapath operatios. 4

5 Datapath ad Cotrol Datapath - performs data trasfer ad processig operatios. Cotrol Uit - Determies the eablig ad sequecig of the operatios. Cotrol iputs Cotrol uit The cotrol uit receives: Exteral cotrol iputs Status sigals Cotrol sigals Status sigals Cotrol outputs Data iputs Datapath The cotrol uit seds: Cotrol sigals Cotrol outputs Describe properties of the state of the datapath Data outputs 5

6 A datapath is specified by: A set of registers. The microoperatios performed o the data stored i the registers. A cotrol iterface: sigals comig ito datapath. 6

7 Datapaths Guidig priciples for basic datapaths: The set of registers Collectio of idividual registers. A set of registers with commo access resources called a register file. A combiatio of the above. Microoperatio implemetatio Oe or more shared resources for implemetig microoperatios: Buses - shared trasfer paths. Arithmetic-Logic Uit (ALU) - shared resource for implemetig arithmetic ad logic microoperatios. Shifter - shared resource for implemetig shift microoperatios. 7

8 Datapath Example Four parallel-load registers. Two mux-based register selectors. Register destiatio decoder. Mux B for exteral costat iput. Buses A ad B with exteral address ad data outputs. ALU ad Shifter with Mux F for output select. Mux D for exteral data iput. Logic for geeratig status bits V, C, N, Z. Write D data Load eable MD select 0 1 MUX D Bus D 8 V C N Z Load Load Load Load G select 4 Zero Detect MF select R0 R1 R2 R3 Decoder D address 2 Costat i Destiatio select MB select Bus A 1 0 MUX B 0 1 MUX F F Bus B 2 2 A data A B H select A B 2 B S 2:0 C i Arithmetic/logic uit (ALU) G A address A select 0 1 MUX 2 3 Fuctio uit Register file S 0 I R Shifter I L 0 H B select B address 0 1 MUX 2 3 B data Address Out Data Out Data I

9 Datapath Example: Performig a Microoperatio Microoperatio: R0 R1 + R2 Apply 01 to A select to place cotets of R1 oto Bus A. Apply 10 to B select to place cotets of R2 oto B data ad apply 0 to MB select to place B data o Bus B. Apply 0010 to G select to perform additio G = Bus A + Bus B Apply 0 to MF select ad 0 to MD select to place the value of G oto BUS D. Apply 00 to Destiatio select to eable the Load iput to R0. Apply 1 to Load Eable to force the Load iput to R0 to 1 so that R0 is loaded o the clock pulse (ot show) The overall microoperatio requires 1 clock cycle. Write D data Load eable MD select 0 1 MUX D Bus D 9 V C N Z Load Load Load Load G select 4 Zero Detect MF select R0 R1 R2 R3 Decoder D address 2 Costat i Destiatio select MB select Bus A 1 0 MUX B 0 1 MUX F F Bus B 2 2 A data A B H select A B 2 B S 2:0 C i Arithmetic/logic uit (ALU) G A address A select 0 1 MUX 2 3 Fuctio uit Register file S 0 I R Shifter I L 0 H B select B address 0 1 MUX 2 3 B data Address Out Data Out Data I

10 Datapath Example: Key Cotrol Actios for Microoperatio Alteratives Perform a shift microoperatio apply 1 to MF select Use a costat i a microoperatio usig Bus B apply 1 to MB select Provide a address ad data for a memory or output write microoperatio apply 0 to Load eable to prevet register loadig Provide a address ad obtai data for a memory or output read microoperatio apply 1 to MD select For some of the above, other cotrol sigals become do't cares Write D data Load eable MD select 0 1 MUX D Bus D 10 V C N Z Load Load Load Load G select 4 Zero Detect MF select R0 R1 R2 R3 Decoder D address 2 Costat i Destiatio select MB select Bus A 1 0 MUX B 0 1 MUX F F Bus B 2 2 A data A B H select A B 2 B S 2:0 C i Arithmetic/logic uit (ALU) G A address A select 0 1 MUX 2 3 Fuctio uit Register file S 0 I R Shifter I L 0 H B select B address 0 1 MUX 2 3 B data Address Out Data Out Data I

11 Arithmetic Logic Uit (ALU) We ow deal with detailed desig of typical ALUs ad shifters. Decompose the ALU ito: A arithmetic circuit: A -bit parallel adder. A block of logic that selects four choices for the B iput to the adder. A logic circuit: Gates to implemet the basic logic operatios. A selector to select which logic operatio to perform. A selector to pick betwee the two circuits. 11

12 -Bit ALU Block Diagram Operatio withi arithmetic or logic Arithmetic or Logic 12

13 ALU 3 steps: 1. Desig arithmetic sectio. 2. Desig logic sectio. 3. Combie both. 13

14 Arithmetic Circuit Desig There are oly four fuctios of B to select as Y i G = A + Y + C i : Y All 0s B B All 1s C i = 0 G = A G = A + B G = A + B G = A 1 C i = 1 G = A + 1 G = A + B + 1 G = A + B + 1 G = A C i A X B S 0 S 1 B iput logic Y -bit parallel adder G = X 1 + Y Y 1 C + i C i C out 14

15 Addig selectio codes to the fuctios of B: 15

16 Parallel Adder We will deal with the desig of ALU bit by bit. 1 bit of ALU = 1 stage of ALU. We desig 1 stage ad repeat it for the rest of the stages. 16

17 Arithmetic Circuit Desig (cotiued) 1 stage of arithmetic sectio of ALU: 17

18 1 Stage of Arithmetic Sectio of ALU S 0 S 1 C i A i B i X i Y i G i C i+1 Yi = B i S 0 + B i S 1 18

19 Arithmetic Sectio of 4-bit ALU 19

20 Logic Circuit Bitwise operatios: AND, OR, XOR, NOT. Use logic gates ad MUX. Oe stage of Logic circuit: 20

21 Combiig Arithmetic ad Logic Sectios 1 stage of arithmetic + 1 stage of logic + 2-to-1 MUX = 1 stage of ALU. A ew sigal S 2 performs the arithmetic/logic selectio The select sigal eterig the LSB of the arithmetic circuit, C i, is coected to the least sigificat selectio iput for the logic circuit, S 0. C i C i C i + 1 A i B i S 0 S 1 A i B i S 0 S 1 Oe stage of arithmetic circuit 0 2-to-1 MUX G i A i 1 S C i B i S 0 Oe stage of logic circuit S 1 Chapter 9 Part 1 S 2 IT321 21

22 Detailed Stage of ALU S 0 S 1 C i A i B i X i Y i C i C i to-1 MUX G i 1 S S 2 22

23 Fuctio Table for ALU 23

24 Shift Operatio Shift right ad shift left. Could be implemeted usig a bidirectioal shift register with parallel load. 1. Load data from Bus to register. 2. Shift. 3. Retur data to Bus. Sequetial. Requires 3 clock pulses. Alterative solutio: use a combiatioal circuit. Use MUXs. Requires 1 clock pulse. 24

25 Combiatioal Shifter Parameters Directio: Left. Right. Number of positios: Sigle bit. Multiple bits. Fillig of vacat positios: May optios depedig o istructio set. Here, will provide iput lies or zero fill. 25

26 4-Bit Basic Left/Right Shifter Serial output L B 3 B 2 B 1 B 0 I R Serial output R I L S M U X S M U X S M U X S M U X S 2 H 3 H 2 H 1 H 0 Serial Iputs (value depeds o shift type): I R for right shift I L for left shift Serial Outputs R for right shift (Same as MSB iput) L for left shift (Same as LSB iput) Shift Fuctios: (S 1, S 0 ) = 00 Pass B uchaged 01 Right shift 10 Left shift 11 Uused 26

27 Datapath Represetatio 1. The registers, ad the multiplexer, decoder, ad eable hardware for accessig them become a register file. 2. The ALU, shifter, Mux F ad status hardware become a fuctio uit. 3. The remaiig muxes ad buses which hadle data trasfers are at the ew level of the hierarchy. Costat i MB select FS V C N Z m m 4 D data Write D address m 2 x Register file A address A data A Bus A B address B data Fuctio uit F 1 0 MUX B Bus B B m Address out Data out Data i MD select 0 1 MUX D 27

28 Simplifyig the Data Path Represetatio Write D data Load eable V C N Z Load Load Load Load G select 4 Zero Detect MF select R0 R1 R2 R3 Decoder D address 2 Costat i Destiatio select MB select Bus A 1 0 MUX B 0 1 MUX F F Bus B 2 2 A data A B H select A B 2 B S 2:0 C i Arithmetic/logic uit (ALU) G A address A select 0 1 MUX 2 3 S 0 I R Shifter I L 0 H Fuctio uit B select B address 0 1 MUX 2 3 Register file B data Address Out Data Out Data I Costat i MB select MD select 0 1 MUX D Chapter 9 Part 1 Bus D IT FS V C N Z m m 4 MD select D data Write D address m 2 x Register file A address A data A Bus A B address B data Fuctio uit F 0 1 MUX D 1 0 MUX B Bus B B m Address out Data out Data i

29 Datapath Represetatio (cotiued) I the register file: Multiplexer select iputs become A address ad B address. Decoder iput becomes D address. Multiplexer outputs become A data ad B data. Iput data to the registers becomes D data. Load eable becomes write. The register file ow appears like a memory based o clocked flip-flops (the clock is ot show). The fuctio uit labelig is quite straightforward except for FS bits: Defie the cotrol sigals to the fuctio uit: MF (1 bit): ALU or Shifter. G (4 bits): Operatio i ALU: S 2, S 1, S 0, ad C i. H (2 bits): Trasfer, shift left or shift right. Costat i MB select 29 FS V C N Z m m 4 MD select D data Write D address m 2 x Register file A address A data A Bus A B address B data Fuctio uit F 0 1 MUX D 1 0 MUX B Bus B B m Address out Data out Data i

30 Defiitio of Fuctio Uit Select (FS) Codes G Select, H Select, ad MF i T of FS Codes Boolea Equatios: MF = FS 3 FS 2 G 3 = FS 3 G 2 = FS 2 G 1 = FS 1 G 0 = FS 0 H 1 = FS 1 H 0 = FS 0 30

31 The Cotrol Word The datapath has may cotrol iputs. The sigals drivig these iputs ca be defied ad orgaized ito a cotrol word. To execute a microistructio, we apply cotrol word values for a clock cycle. Addresses for the data read from register file. Fuctio performed. Addresses for the data writte to register file. Exteral data. 31

32 The Cotrol Word Fields D A AA BA M B FS M D R W Cotrol word Fields DA D Address AA A Address BA B Address MB Mux B FS Fuctio Select MD Mux D RW Register Write 3 bits each. Meas we have up to 8 registers. 2 d parameter to fuctio from register (0) or a costat (1). Load to register exteral data or result of fuctio. 32

33 Cotrol Word Block Diagram R W 0 Write D data D A D address 8 x Register file AA A address A data B address B data BA Costat i MB 6 Bus A 1 0 MUX B Bus B Address out Data out A B Cotrol word V C N Z Fuctio uit 5 4 FS 3 2 Data i 0 1 MD 1 MUX D Bus D 33

34 Cotrol Word Ecodig Ecodig of Cotrol W D A, AA, B A MB FS MD R W Fuctio Code Fuctio Code Fuctio Code Fuctio Code Fuctio Code R Register 0 F A 0000 Fuctio 0 No write 0 R Costat 1 F A Data I 1 Write 1 R F A + B 0010 R F A + B R F A + B 0100 R F A + B R F A R F A 0111 F A B 1000 F A B 1001 F A B 1010 F A 1011 F B 1100 F sr B 1101 F sl B

35 Example Microoperatios for the Datapath - Symbolic & Biary Represetatio Micr o- op eratio D A A A B A M B F S M D R W R 1 R 2 R 3 R 4 s l R6 R 7 R R 1 R Data out R 3 R 4 D ata i R 5 0 R1 R2 R3 Register F = A + B + 1 Fuctio Write R 4 R 6 Register F = sl B Fuctio Write 100 xxx R 7 R 7 F = A + 1 Fuctio Write xxx x R 1 R 0 Costat F = A + B Fuctio Write xxx R 3 Register No Write xxx xxx xxxx x 0 R 4 Data i Write 100 xxx xxx x xxxx 1 1 R 5 R 0 R 0 Register F = A B Fuctio Write

36 Biary Represetatio 36