Overview EECS Components and Design Techniques for Digital Systems. Lec 15 Addition, Subtraction, and Negative Numbers. Positional Notation

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1 Overview EEC 5 Compoets ad Desig Techiques for Digital ystems Lec 5 dditio, ubtractio, ad Negative Numbers David Culler Electrical Egieerig ad Computer cieces Uiversity of Califoria, erkeley Recall basic positioal otatio iary dditio Full dder (oolea Logic Revisited) Ripple Carry Carryselect adder Carry lookahead adder iary Number Represetatio ig & Magitude, Oes Complemet, Twos Complemet /6/27 EEC5Fa7 L5 additio Maipulatig represetatios of umbers Example (from 2 d grade) equece of decimal digits (radix ) Positio represets sigificace (most > least) Carry ito ext positio 3to2 coversio at each step Results may be oe digit loger, but assumed you could make room for it Positioal Notatio equece of digits: D k D k2 D represets the value D k k D k2 k2 D where D i {,, } is the base or radix of the umber system Example: 2, Ca covert from ay radix to ay other 2 = 3 = D 6 CE8 6 = = = = 286 /6/27 EEC5Fa7 L5 additio /6/27 EEC5Fa7 L5 additio

2 Computer Number ystems We all take positioal otatio for grated D k D k2 D represets D k k D k2 k2 D where {,, } We all uderstad how to compare, add, subtract these umbers dd each positio, write dow the positio bit ad possibly carry to the ext positio Computers represet fiite umber systems Geerally radix 2 How do they efficietly compare, add, sub? How do we reduce it to etworks of gates ad FFs? Where does it break dow? Maipulatio of fiite represetatios does t behave like same operatio o coceptual umbers /6/27 EEC5Fa7 L5 additio Usiged Numbers dditio Example: 3 2 = 5 => tart with a truth table ad go from there /6/27 EEC5Fa7 L5 additio Usiged biary additio Is just additio, base 2 dd the bits i each positio ad carry How do we build a combiatioal logic circuit to perform additio? iary dditio: Half dder i i i i Carry um um Carry i i um = i i i i = i i Halfadder chematic i i Carry = i i Fulldder (derivatio) Co Ci = CI xor xor = CI CI = CI ( ) CI CI CI ut each bit positio may have a carry i 3 uary iputs F 2 biary outputs /6/27 EEC5Fa7 L5 additio /6/27 EEC5Fa7 L5 additio

3 Full dder Ripple Carry Co CI Ci? 3 C3 2 C2 C CI Now we ca coect them up to do multiple bits /6/27 EEC5Fa7 L5 additio /6/27 EEC5Fa7 L5 additio Full dder from Half dders (little aside) tadard pproach: 6 Gates CI CI Delay i the Ripple Carry dder late arrivig sigal Critical delay: the propagatio of carry from low to high two gate delays to compute lterative Implemetatio: 5 Gates C CI Half dder Half dder CI CI ( ) stage adder 2 C C CI ( xor ) = CI CI /6/27 EEC5Fa7 L5 additio /6/27 EEC5Fa7 L5 additio fial sum ad carry

4 Ripple Carry Timig Critical delay: the propagatio of carry from low to high order stages, C Valid, C2 Valid 2, C3 Valid 3, C Valid Recall: VirtexE CL CL = logic cells (LC) i two slices LC: iput fuctio geerator, carry logic, storage ele t 8 x 2 CL array o 2E worst case additio T T2 T T6 T8 T: Iputs to the adder are valid T2: tage carry out (C) T: tage carry out (C2) T6: tage 2 carry out (C3) 2 delays to compute sum but last carry ot ready util 6 delays later T8: tage 3 carry out (C) /6/27 EEC5Fa7 L5 additio /6/27 6x EEC5Fa7 sychroous L5 RM additio FF or latch dders (cot.) Carry elect dder Ripple dder c7 c6 c5 c c3 c2 b a c b7a7 b6a6 b5a5 b a F b3a3 b2a2 ba ba c s7 s6 F Ripple adder is iheretly slow because, i geeral s7 must wait for c7 which must wait for c6 c s c8 b7a7 b6a6 b5a5 ba F s3 s2 s s T α, Cost α How do we make it faster, perhaps with more cost? Classic approach: Carry Lookhead Or use a MUX!!! /6/27 EEC5Fa7 L5 additio s7 s6 s5 s T = T ripple_adder / 2 T MUX T =.5 * T ripple_adder () * T MUX /6/27 EEC5Fa7 L5 additio

5 Exteded Carry elect dder Carry elect dder Performace b5b2 a5a2 bb8 aa8 b7b a7a b5b2 a5a2 bb8 aa8 b7b a7a cout bit dder bit dder bit dder bit dder bit dder bit dder b3b a3a bit dder ci cout bit dder bit dder bit dder bit dder bit dder bit dder b3b a3a bit dder ci What is the optimal # of blocks ad # of bits/block? If # blocks too large delay domiated by total mux delay If # blocks too small delay domiated by adder delay per block N stages of N bits /6/27 EEC5Fa7 L5 additio T α sqrt(n), Cost 2*ripple muxes Compare to ripple adder delay: T total = 2 sqrt(n) T F T F, assumig T F = T MUX For ripple adder T total = N T F crossover at N=3, Carry select faster for ay value of N>3. Is sqrt(n) really the optimum? From right to left icrease size of each block to better match delays Ex: 6bit adder, use block sizes [ ] How about recursively defied carry select? /6/27 EEC5Fa7 L5 additio oucemets Readig Katz 5.6 ad ppedix Mid III will just stay put i fial slot o more fussig with it. Project demo at Lab Lecture friday Do t hedge o lab workload reportig It matters to us ad is NOT a egative i your grade Lab5 CP CP2 cruch It should lighte Do t hesitate to get guidace o the specifics of your approach from the Ts. They are there to help. Lab5 solutio walkthru Friday after lab lecture What really happes with the carries b a c7 c6 c5 c c3 c2 c F s7 s6 c s Cout Carry actio i Ci kill Gi Ci ~Ci Propagate i Ci ~Ci propagate i Pi Ci geerate i Carry Geerate Gi = i i must geerate carry whe = = Carry Propagate Pi = i xor i carry i will equal carry out here /6/27 EEC5Fa7 L5 additio ll geerates ad propagates i parallel at first stage. No ripple. /6/27 EEC5Fa7 L5 additio

6 Carry Kill / Prop / Ge example Carry Look head Logic c7 c6 c5 c c3 c2 Carry Geerate Gi = i i must geerate carry whe = = F Carry Propagate Pi = i xor i carry i will equal carry out here s7 s6 s um ad Carry ca be reexpressed i terms of geerate/propagate: K P G P K P P G i = i xor i xor Ci = Pi xor Ci Ci = i i i Ci i Ci Ci Pi i = i i Ci (i i) = i i Ci (i xor i) = Gi Ci Pi Gi Ci Pi Ci /6/27 EEC5Fa7 L5 additio /6/27 EEC5Fa7 L5 additio ll Carries i Parallel CL Implemetatio Reexpress the carry logic for each of the bits: C = G P C i i Ci gate delay 2 gate delays dder with Propagate ad Geerate Outputs C2 = G P C = G P G P P C C3 = G2 P2 C2 = G2 P2 G P2 P G P2 P P C gate delay Icreasigly complex logic C = G3 P3 C3 = G3 P3 G2 P3 P2 G P3 P2 P G P3 P2 P P C Each of the carry equatios ca be implemeted i a twolevel logic etwork Variables are the adder iputs ad carry i to stage! C P G C P P G P G C C2 C P P P2 G P P2 G P2 G2 C3 C P P P2 P3 G P P2 P3 G P2 P3 G2 P3 C /6/27 EEC5Fa7 L5 additio /6/27 EEC5Fa7 L5 additio G3

7 How do we exted this to larger adders? Cascaded Carry Lookahead Faster carry propagatio bits at a time ut still liear Ca we get to log? Compute propagate ad geerate for each adder LOCK 7 3 C [52] [52] 6 C [8] [8] bit dder 2 C [7] [7] bit dder 8 C [3] [3] C bit dder bit dder P G P G P G @ [52] [8] @3 P 3 G 3 C 3 P 2 G 2 C 2 P G C P G C 6 C C Lookahead Carry P 3 bit adders with iteral carry lookahead secod level carry lookahead uit, exteds lookahead to 6 bits Oe more level to 6 bits /6/27 EEC5Fa7 L5 additio /6/27 EEC5Fa7 L5 additio Tradeoffs i combiatioal logic desig o what about subtractio? Time vs. pace Tradeoffs Doig thigs fast requires more logic ad thus more space Example: carry lookahead logic imple with lots of gates vs complex with fewer rithmetic Logic Uits Critical compoet of processor datapath Develop subtractio circuit usig the same process Truth table for each bit slice orrow i from slice of lesser sigificace orrow out to slice of greater sigificace Very much like carry chai Homework exercise Iermost "loop" of most computer istructios /6/27 EEC5Fa7 L5 additio /6/27 EEC5Fa7 L5 additio

8 Fiite represetatio? /6/27 EEC5Fa7 L5 additio What happes whe > 2 N? Overflow Detect?» Carry out What happes whe <? Negative umbers? orrow out? Number ystems Desirable properties: Efficiet ecodig (2 bit patters. How may umbers?) Positive ad egative» Closure (almost) uder additio ad subtractio Except whe overflow» Represetatio of positive umbers same i most systems» Major differeces are i how egative umbers are represeted Efficiet operatios» Compariso: =, <, >» dditio, ubtractio» Detectio of overflow lgebraic properties?» Closure uder egatio?» == iff == Three Major schemes: sig ad magitude oes complemet twos complemet /6/27 (excess otatio) EEC5Fa7 L5 additio Which oe did you lear i 2 d grade? ig ad Magitude = = 6 7 High order bit is sig: = positive (or zero), = egative Remaiig low order bits is the magitude: () thru 7 () Number rage for bits = / 2 Represetatios for? Operatios: =, <, >,,??? /6/27 EEC5Fa7 L5 additio Example: N = Oes Complemet it maipulatio: simply complemet each of the bits > lgebraically N is positive umber, the N is its egative 's complemet N = (2 )N 2 Example: 's complemet of 7 i 's comp. /6/27 EEC5Fa7 L5 additio

9 Oes Complemet o the umber wheel ubtractio implemeted by additio & 's complemet ig is easy to determie Closure uder egatio. If ca be represeted, so ca till two represetatios of! If = the is ==? dditio /6/27 is almost clockwise EEC5Fa7 advace, L5 additio like usiged = = Twos Complemet umber wheel Easy to determie sig (?) 8 7 Oly oe represetatio for dditio ad subtractio just as i usiged case imple compariso: < iff < Oe more egative umber tha positive umber oe umber has o additive iverse /6/27 EEC5Fa7 L5 additio 2 3 = = Twos Complemet (algebraically) N* = 2 N 2 = Example: Twos complemet of 7 sub 7 = = repr. of How is additio performed i each umber system? Example: Twos complemet of sub 2 = = Operads may be positive or egative it maipulatio: = repr. of 7 Twos complemet: take bitwise complemet ad add oe > > (represetatio of ) > > (represetatio of 7) /6/27 EEC5Fa7 L5 additio /6/27 EEC5Fa7 L5 additio

10 ig Magitude dditio Operad have same sig: usiged additio of magitudes Oes complemet additio Perform usiged additio, the add i the edaroud carry result sig bit is the same as the operads' sig 3 7 () 3 7 () Operads have differet sigs: subtract smaller from larger ad keep sig of the larger Ed aroud carry 3 Ed aroud carry 3 /6/27 EEC5Fa7 L5 additio /6/27 EEC5Fa7 L5 additio Whe carry occurs Why does edaroud carry work? 2 3 = Recall: N = (2 ) N Edaroud carry work is equivalet to subtractig 2 ad addig M N = M N = M (2 N) = (M N) 2 (whe M > N) = M N where M > N M N M (N) = M N = (2 M ) (2 N ) = 2 [2 (M N)] after ed aroud carry: = 2 (M N) M N < 2 this is the correct form for represetig (M N) i 's comp! /6/27 EEC5Fa7 L5 additio /6/27 EEC5Fa7 L5 additio

11 Twos Complemet dditio Twos Complemet umber wheel Perform usiged additio ad Discard the carry out. Overflow? 3 7 () = = M N where N M 2 impler additio scheme makes twos complemet the most commo choice for iteger umber systems withi digital systems /6/27 EEC5Fa7 L5 additio M N whe N > M /6/27 EEC5Fa7 L5 additio 2s Comp: igore the carry out M N whe N > M: M* N = (2 M) N = 2 (N M) Igorig carryout is just like subtractig 2 M N where N M 2 M (N) = M* N* = (2 M) (2 N) = 2 (M N) 2 fter igorig the carry, this is just the right twos compl. represetatio for (M N)! /6/27 EEC5Fa7 L5 additio 2s Complemet Overflow How ca you tell a overflow occurred? dd two positive umbers to get a egative umber or two egative umbers to get a positive umber = 8! 2 = 7! /6/27 EEC5Fa7 L5 additio 3 7 6

12 2s comp. Overflow Detectio 2s Complemet dder/ubtractor el el el el Overflow Overflow No overflow /6/27 EEC5Fa7 L5 additio 5 8 No overflow Overflow occurs whe carry i to sig does ot equal carry out CI CI CI CI 3 2 Overflow = () = /6/27 EEC5Fa7 L5 additio dd/ubtract ummary Circuit desig for usiged additio Full adder per bit slice Delay limited by Carry Propagatio» Ripple is algorithmically slow, but wires are short Carry select imple, resourceitesive Excellet layout Carry lookahead Excellet asymptotic behavior Great at the board level, but wire legth effects are sigificat o chip Digital umber systems How to represet egative umbers imple operatios Clea algorithmic properties 2s complemet is most widely used Circuit for usiged arithmetic ubtract by complemet ad carry i Overflow whe ci xor cout of sigbit is /6/27 EEC5Fa7 L5 additio