DESIGN AND IMPLEMENTATION OF IMPROVED AREA EFFICIENT WEIGHTED MODULO 2N+1 ADDER DESIGN

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1 ARPN Joural of Egieerig ad Applied Scieces Asia Research Publishig Network (ARPN). All rights reserved. DESIGN AND IMPLEMENTATION OF IMPROVED AREA EFFICIENT WEIGHTED MODULO 2N+ ADDER DESIGN Dhaabal R., Roshi Guerkar ad Bharathi V. 2 School of Electroics Egieerig, VIT Uiversity, Vellore, Tamil Nadu, Idia 2 GGR College of Egieerig ad Techology, Aa Uiversity, Vellore, Tamil Nadu, Idia rdhaabal@vit.ac.i ABSTRACT I this, we proposed improved area - efficiet weighted modulo 2 + adder. This is achieved by modifyig existig dimiished-, weighted modulo 2 + adder to icorporate simple correctio schemes.proposed adder is desiged usig area efficiet parallel prefix structure ad carry select adder. Proposed adder ca produce modulo sums withi the rage (0, 2 ) that is more tha the rage (0, 2-) produced i existig dimiished- modulo 2 + adders. Modular adder is desiged usig verilog HDL ad implemeted usig 45 m techology ad the area required by the proposed adder is lesser tha the existig dimiished-,weighted modulo 2 + adder. Keywords: modulo 2 + adder, residue umber system, VLSI desig. INTRODUCTION For efficiet carry free arithmetic computatio, Residue umber system has bee employed i DSP applicatios as the computatio for each residue chael ca be idepedetly doe without carry propagatio. As compared to biary based system, RNS based system ca achieve higher speed-up. Thats why RNS based system are widely used i DSP applicatio, FIR filter ad commuicatio compoets. Arithmetic modulo 2 + adder is the commo RNS operatio i pseudoradom umber geeratio ad cryptography. The moduli 2 + is the commoly used moduli. There are may existig methods to speed up the weighted modulo 2 + additio. Depedig o iput/output data represetatio this methods are classified ito two categories amely dimished- ad weighted. I Dimiished-, each iput ad output operad is decreased by as compared to weighted oe. Therefore, i dimiished- modulo adder oly -bit operads are eeded that leads to faster ad smaller compoet. However this icurs a overhead due to traslator from/to biary weighted system. O the other had i weighed modulo adder, (+) bit operads are required that avoids the use of traslator but leads to more area as compared to dimiished- modulo adder. The geeral operatios for modulo 2 + additio are discussed i [3]. The authors proposed efficiet parallel prefix adders for dimiished- modulo 2 + additio i [3] ad [4]. For improvemet of area-time ad time-power products, circular carry selectio scheme was used for fial modulo additio [3, 4]. However the hardware for decreasig or icreasig the iputs/outputs by is omitted i the literature. There is the eed of zero detectio circuit also as the value zero is ot allowed i the dimiished- modulo 2 + additio. This leads to the icrease i the hardware cost. I [], a uified approach for weighted ad dimiished- modulo 2 + additio is proposed. This approach is based o makig the modulo 2 + additio of two (+)-bit iput umbers A ad B cogruet to Y+U+, where Y ad U are two -bit umbers. Thus to perform weighted modulo 2 + additio of Y ad U ay dimiished - modulo adder ca be used. I [2], the traslators are used to decrease the sum of two -bit iputs A ad B by ad the weighted modulo 2 + additio is performed usig dimiished- adders. I this brief,improved area efficiet weighted modulo 2 + adder desig usig dimiished- adder with simple correctio schemes is proposed ad is modified for more area efficiet usig Sklasky carry select adder (SK CSLA). The rest of the brief is orgaised as follows.i sectio II Backgroud of adders is give. I sectio III, review of desig of two previous weighted modulo 2 + adder is preseted. Proposed area efficiet weighted modulo 2 + adder is preseted i sectio IV. I sectio V sythesis result ad comparisos are give ad sectio VI cocludes this brief. Review of two weighted modulo 2 + adder A ad B are two (+) bit umbers where 0 A, B 2, the values of dimiished- of A ad B are deoted by A*=A- ad B*=B- respectively. The dimiished- sum ca be computed as S*= S- 2 += A+B- 2 += A*+B* 2 + (~cout) () Where X z is defied as modulo Z of X ad (~ cout) is defied as the iverted ed aroud carry of dimiished- modulo 2 + adder. Vergos ad efstathiou [] I [], first computatio of the cogruet modulo sum of A+B is doe to produce Y ad U ad the fial modulo sum is computed by ay dimiished- modulo adder as follows. Suppose A ad B are two (+)-bit iput umbers. i.e. A = a a -,..., a 0 = a 2 + A ad B = b b -,..., b 0 = b 2 + B, where 0 A,B 2, ad A ad B are two - bit umbers; the 2569

2 ARPN Joural of Egieerig ad Applied Scieces Asia Research Publishig Network (ARPN). All rights reserved. A + B 2 + = A + B + D = Y + U (2) I (2), D = (~c +) + (~ s ), which is equal to... ~c + ~s, where c + = a b ad s = a ^ b is the bit of D with biary weights 2 ad 2 0, respectively. The first step of (2) calculates modulo 2+ carry save additio, givig the sum vector U ad carry vector where Y = y 2 y 3... y 0 (~y ) ad U = u u 2... u 0. Y ad U are produced by addig A, B ad D respectively. The values of D with biary weights of 2 2 through 2 are all ; therefore, adders to produce the carries ad sums are desiged usig OR ad XNOR gates for every bit positio directly. I the bits of D with biary weights 2 ad 2 0, the adders should be modified to accept the values (~s ) ad (~c +), respectively. Vergos ad bakalis [2] I [2] the sum of the two -bit iputs A ad B is subtracted by to produce the dimiished- values A ad B ad modulo 2 sum of A ad B ca be computed by ay dimiished- architecture, as follows: A + B = A + B 2 + ~cout. (3) The value (~cout) is the iverted ed-aroud carry produced by A + B. The architecture proposed i [] makes use of a costat time operator, which is formed by the use of simplified carry-save adder stage, leadig to efficiet modulo 2 + adders. The architecture proposed i [2] ca be applied i the desig of area-efficiet residue geerators ad multioperad modulo adders. However i [], the values that are subtracted by the iputs A ad B are ot costats. I [2], the way to implemet the traslator for decreasig the sum of two iputs A ad B by was ot metioed. Further, i [2], the rages of two iputs A ad B are less tha the oe proposed i [] (i.e., {0, 2 - } versus {0, 2 }). To provide remedy o these problems, area-efficiet weighted modulo 2 + adder desig usig parallel prefix structure ad sklasky carry select adder is proposed i the sectio 4. Backgroud RNS ad modular additio RNS is defied as group of co-prime modular radixes {m, m2...m N} where N>GCD (m i,m j) = i j i, j=, 2...N. The iteger X i {0, M} ca be represeted with respect to the modulus m i that is {x, x 2...x N}. Let a a 2...a N, b b 2...b ad c c 2...c be the RNS represetatio of itegers.accordig to Gaussia modular algorithms, if c i= a i b i m we ca get C= A B M where represet subtractio, additio ad multiplicatio. A, B ad C are i the rage [0, M]. For itegers A ad B i the rage of [0, m] modulo m additio is defied as C= A+B m =A+B A+B<m A+B-m A+B>m If C= A+B m ad the bit width of the modular adder is -bit, where = [log 2m]. [] Parallel prefix adders Parallel prefix adders are obtaied from carry look ahead structure. Tree Structure form is used to icrease the speed of arithmetic operatio. Parallel prefix adders are fastest adders ad are used for high performace. Parallel prefix adder ivolves three stages: a) Pre processig b) Carry geeratio c) Post processig Pre- processig stage I this, the sigals are computed, geerated ad propagate to each pair of iput U ad Y. This sigals are give by P i=u i ^Yi G i= U i ad Yi Carry geeratio etwork I this stage carries are computed correspodig to each bit. Executio of these operatios is carried out i parallel. After the carries are computed i parallel they are segmeted ito smaller groups. Carry geerate ad propagate are used as itermediate sigals which are give by P i:j=p i:k+ ad P k:j G i:j=g i:k+ or (P ik+ ad G k:j) Post processig This is the fial step to calculate summatio of iput bits.sum bits are calculated as: C i- = (P i ad C i) or G i S i= P i xor C i- [5] Proposed improved area - efficiet weighted modulo 2 + adder Istead of subtractig the sum of A ad B by D, which is ot a costat as proposed i [], the costat value - (2 + ) is used which is to be added by the sum of A ad B. The two iputs A ad B are i the rage {0, 2 }, which is more tha {0, 2 - } as proposed i [2]. I the followig, the desigs of proposed weighted modulo 2 + adder is preseted. Give two ( + )-bit iputs A = a a,..., a 0 ad B = b b,..., b 0, where 0 A,B 2. The weighted modulo 2 + of A + B ca be represeted as follows: A + B 2 + = A + B (2 + ), if (A + B) > 2 A + B, otherwise. (4) Equatio (4) ca be stated as A+B = A+B-(2 +) 2, if (A+B)>2 A+B-(2 +) 2 + (2 +) 2, otherwise (5) This ca be expressed as 2570

3 ARPN Joural of Egieerig ad Applied Scieces Asia Research Publishig Network (ARPN). All rights reserved. A+B = A+B - (2 +) 2 if (A+B)>2 A+B - (2 +) 2 +, otherwise (6) From (6), it ca be oted that the value of weighted modulo 2 + additio ca be obtaied by first subtractig the sum of A ad B by 2 + ad the usig dimiished- adder to get the fial modulo sum by makig the iverted ed aroud carry as carry-i. The weighted modulo 2 + additio of A ad B ca be calculated as follows: Deotig U ad Y as the sum ad carry vector of the summatio of A, B ad - (2 +) where Y= y -2 y y 0 (~y -) ad U=u - u u 0, the modulo additio ca be expressed as: weighted modulo 2 + adder is show. The weighted modulo 2 + adder is ehaced for more area efficiecy by desigig the dimiished - adder usig sklasky carry select adder (SK CSLA)as show i Figure-3. I 6- bit sk csla show i Figures 3 2, 3, 4, 5 bit sklasky parallel prefix structure are used for carry i 0 ad output of this is fed to add oe circuit which is used to icremet the output of 2, 3, 4, 5 bit sklasky structure by. The fial carry out is computed by selectig the carry out of the 2, 3, 4, 5sklasky ad add oe circuits idepedetly usig Mux. [2]. A+B-(2 +) 2 = (2 i * (a i + b i)) +2 - * (2a + 2b +2b +a -+b -) = (2 i * (a i + b i +)) *(2a +2b +a -+b -+) 2 = (2 i * (2y+u)) *(2a + 2b +a -+ b - +) 2 For i=0 to -2, the values of U i ad Y i ca be expressed as U i = ~ (a i ^ b i) ad Y i= a i bi respectively. Sice Y ad U are bit, the value of y - ad u - are calculated usig a, b, a - ad b -. It should be oted that 0 A, B 2, which meas if a =a -= or b =b -=, the value of A or B will exceed the rage of {0, 2 }. Thus this iput combiatios are ot allowed ad ca be viewed as do t care coditio.the truth table for geeratig y -, u - ad FIX is give i Table-. The reaso for FIX is that the value of y - ca be equal to 2(e. g a = b = ad a -=b -=0) which caot be represeted by bit lie. Therefore value of y - is set to ad remaiig value of carry i.e. is set to FIX. FIX is wired -or with the carry out of Y+U (i.e. cout) to be iverted ed aroud carry as carry i for dimiished - additio. Whe y -=2, FIX= otherwise FIX=0. [] (a) (b) Accordig to Table I y -= (a b a - b -), u - = ~ (a -^b -) ad FIX = a b b a - a b - respectively. Proposed weighted modulo 2 + additio of A ad B is equivalet to A+B = A+B-(2 + ) 2 = Y+U 2 + ~ (cout FIX). (7) Examples for proposed weighted modulo 2 + additio are give as follows: (c) Example-: suppose =4, A=6 0= ad B =5 0=0 2, respectively. Step ) (A+B)-(2 +) =>Y=0 2 U=0000 2, FIX=. Step 2) Y+U =0 2, Cout = 0, => Y+U+ ~ (Cout FIX) = 0 2 = 6+5 7=4 0 The architecture for weighted modulo 2 + adder based o sklasky parallel prefix structure is show i Figure-. The sigal of FIX ca be computed i parallel with the traslatio to Y+U, leadig to efficiet correctio. I Figure-2 Dimiished- adder based o sklaky parallel prefix structure with correctio circuits for (d) Figure-. (a) Architecture of weighted modulo 2 + adder with the correctio scheme. (b) Architecture of the 257

4 ARPN Joural of Egieerig ad Applied Scieces Asia Research Publishig Network (ARPN). All rights reserved. traslator-(2 +). (c)architecture of the correctio scheme. (d) Architecture of FAF ad FA+, respectively. [] (a) (b) (c) Figure-2. (a) Dimiished- adder based o the sklasky-style parallel prefix structure for weighted modulo 2 + adder (b) diamod odes ad square ode respectively. (c) black operator ad white ode respectively. [] Simulatio, sythesis results ad compariso Verilog structurig hardware descriptio laguage is used to desig proposed adder ad the existig work ad are implemeted usig 45 m techology. The simulated output of 6 bit SK CSLA is show i Figure-4. The values of the area ad power for the dimiished- adder desiged usig sklasky ad sklasky carry select adder are show i Table-2 ad Table-3 respectively. The compariso for the various modulo 2 + adder is show i Figure-5. The dimiished adder based o Sklasky style parallel prefix structure ad SK CSLA with correctio circuits for weighted modulo 2 + adder are show i Figure-2(a) ad Figure-3 respectively. The square ( ) ad the diamod ( ) odes deote the pre-processig ad post-processig stages of the operads, respectively. The black odes evaluate the prefix operator ad the white odes pass the uchaged sigal to the ext level. The detailed iformatio of four odes is give i Figure-2. (b), (c). 2572

5 ARPN Joural of Egieerig ad Applied Scieces Asia Research Publishig Network (ARPN). All rights reserved. a8 b8 a7 b7 U[5:] Y[4:0] U[0:7] Y[9:8] U[6:4] Y[5:3] U[3:2] Y[2:] U[:0] (Y[0],~Y[5]) CORRECTION 5: SK :7 SK 6:4 SK 3:2 SK :0 SK C0 FIX MUX MUX MUX MUX C3 C2 C cout U[5:0] Y[5:0] RCA RESULT Figure-3. 6-bit sklasky carry select adder for proposed weighted modulo 2 + adder where RESULT represets the fial modulo additio. Table-. Truth table for geeratig y -, u - ad FIX (*coditios whe y -=2). A b a- b- u- y- FIX X X X * 0 X X X * 0 0 X X X 0 X X X 0 0 * 0 X X X 0 X X X X X X Bit Table-2. Area values for various modulo 2 + adder (UNITS: um.sq). Sklasky parallel prefix structure based modulo 2 + adder Sklasky carry select adder based modulo 2 + adder

6 ARPN Joural of Egieerig ad Applied Scieces Asia Research Publishig Network (ARPN). All rights reserved. Bit Table-3. Power values for various modulo 2 + adder (UNITS: W). Sklasky parallel prefix structure based modulo 2 + adder Sklasky carry select adder based modulo 2 + adder additio. IEEE Tras. Circuit s syst. II, exp briefs. 55(0): [2] H.T. Vergos ad D. Bakalis O the use of dimiished - adders for weighted modulo 2 + arithmetic compoets. I: proc. th EUROMICRO Cof. Digit. Syst. Des. Archit, Methods tools. pp Figure-4. Simulated output for 6 bit SK CSLA. [3] S-H. Li ad M.-H. Sheu VLSI desig of dimiished-oe modulo 2 + adder Usig circular carry selectio, IEEE tras. circuits syst II expbriefs. 55: [4] T.-B juag M.-Y. Tsai ad C.-C. Chiu Correctios o VLSI desig of dimiished-oe modulo 2 + adder usig circular carry selectio. IEEE tras. circuits syst II exp briefs. 56(3): [5] M. sir Depth-size trade - offs for parallel prefix computatio. I: Joural of algorithms. 7, pp Figure-5. Area compariso of modular adder based o differet adder desig. CONCLUSIONS I this brief a improved area efficiet weighted modulo 2 + adder is proposed. This is achieved by modifyig existig weighted modulo 2 + adder by desigig the dimiished- adder used with more area efficiet sklasky carry select adder. The proposed adders ca perform weighted modulo 2 + additio ad produce sums withi the rage {0, 2 }. Sythesis result shows that the weighted modulo 2 + adder desiged usig SK CSLA ca outperform weighted modulo 2 + adder desiged usig sklasky adder i terms of area. ACKNOWLEDGEMENT Roshi Guerkar would like to thak Mr. R. Dhaabal, Assistat Professor (Seior Grade), SENSE who had bee guidig me throughout the project ad helped me i techical issues about the paper. REFERENCES [] H.T Vergos. ad C.Efstathiou A uifyig approach for weighted ad dimiished- modulo 2 + [6] H.T Vergos, C. Efstathiou ad D. Nikolos Dimiished-oe modulo 2 + adder desig. IEEE tras. Comput. 5(2): [7] C. Efstathiou, H.T. vergos ad D. Nikolos Modulo 2 + adder desig usig select prefix blocks. IEEE Tras. Comput. 52(): [8] A. A. Hiasat High-speed ad reduced-area modular adder structures for RNS. IEEE Tras. Comput. 5(): [9] G. Jaberipur ad S. Nejati. 20. Balaced miimal latecy RNS additio for moduli set, (2^+, 2^-) i Proc. 8th It. Cof. Systems, Sigals ad Image Processig (IWSSIP). pp. -7. [0] A uifyig approach for weighted ad dimiished- modulo 2^+ additio. IEEE Tras. Circuits Syst. II, Exp. Briefs. 55(0): [] 200. Improved area efficiet weighted modulo 2 + adder desig with simple correctio schemes. IEEE trasactios o circuits ad systems-ii: express briefs. 57(3). 2574

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