On the Realization of Online Ternary Testable Circuit

Transcription

1 Iteratioal Joural of Sciece ad Techology Volume 1 No. 4, pril, 2012 O the Realizatio of Olie Terary Testable Circuit Naushi Nower 1, hsa Raja Chowdhury 2 1 Istitute of Iformatio Techology, Uiversity of Dhaka, Dhaka, agladesh 2 Departmet of Computer Sciece & Egieerig, Uiversity of Dhaka, Dhaka, agladesh STRCT Terary Reversible logic got the attetio i the recet years for its applicatios i differet sectios of Reversible Logic Sythesis. Desigig olie testable circuits are also cosidered as the promiet field of research i this domai. This paper presets a ovel idea of Olie Testable Terary Reversible Circuits desig, where architecture is capable of testig reversible terary etwork i real-time (olie). The error detectio uit, a compoet of the proposed desig, is also desiged with reversible gates, for which the etire circuit is cosidered reversible. The evaluatio of the proposed desig is carried out with example circuits i terms of well-kow desig parameters to show the effectiveess ad compactess of the circuit. Keywords: Garbage output, Miterm, Terary olie testig. 1. INTRODUCTION Ladauer [1, 2] proves that, logic computatios that are ot reversible, geerate heat kt*l2 for every bits of iformatio that is lost, where k is the oltzma s costat ad T is the temperature [2]. reversible logic gate is a k-iput, k-output (deoted k*k) device that maps each possible iput patter ito a uique output patter [3]. eett showed that ktl2 eergy dissipatio would ot occur, if a computatio were carried out i a reversible way [1]. Reversible computatio i a system ca be performed if the system is composed of reversible gates. Testig the reversible circuits is a major dispute i today s research because the levels of logic are sigificatly higher tha the stadard logic [3]. Olie testability is a feature of a circuit that pledges the testig of the circuit at the time the computatio is performed. Our proposed work cocetrates o the desig of terary testable block usig covetioal terary reversible gates. The proposed block is versatile ad extedable as it ca be used to realize ay arbitrary sized Terary ESOP expressio. Good umber of research works have bee performed recetly [4-8], focus o biary reversible circuit testig. However, oly few of them [9-10] focus o the terary circuit testig. Rest of the paper is orgaized as follows: Sectio 2 provides some asic Defiitio ad Literature Review regardig Terary Reversible Logic ad Olie Testig. The proposed idea is itroduced i Sectio 3 where evaluatio of the proposed desig techique is thoroughly discussed with examples i Sectio 4. The paper cocludes with observatios ad suggestios for future study i Sectio LITERTURE REVIEW I this sectio we discuss some terms ad defiitios used i this paper alog with some existig methods. Defiitio 1: Olie Testability is the ability of a circuit to test a reversible block at the time the circuit is performig a operatio. It is the uique feature of reversible circuit first proposed i [3]. The authors of [3] proposed three reversible logic gates: R1, R2 ad R3 (show i Figure 1), where R1 ad R2 ca be used i pairs to desig testable reversible logic circuits, ad R3 that is used to costruct two pair two rail checker [8]. IJST 2012 IJST Publicatios UK. ll rights reserved. 197

2 10] for calculatig the cost of a terary expressio. I our proposed architecture, we have show more efficiet desig tha the existig. The proposed TR1 ad TR2 [9, 10] are show i Figure 2 ad two pair rail checker is depicted i Figure 3. (a)r 1 Gate Defiitio 2: Terary Quatum Logic is the simplest itroductio of multi-valued logic which is also referred to as 3VL.To defie terary logic, let T = {0, 1, 2}. terary reversible logic circuit with iputs ad outputs is also called a -qudit terary reversible gate ca operate o terary values. (b) R 2 Gate Toffoli M P N L (c) R 3 Gate C C Q Figure 1: Olie Testable Reversible Logic Gates [3] (a) TR 1 lock The first gate R1 is used for implemetig arbitrary fuctios while the secod gate R2 is employed to icorporate o-lie testability features ito the circuit. It ca be verified that the iput patter of these gates ca be uiquely determied from the particular output patter. pplicatios of testable block [3] are sketched i [8] o ripple carry adder ad carry skip adders. They have show the implemetatio of their testable block [3] o the subset of MCNC bechmark circuit. ut the desigs do ot have ay implicatio o multi valued logic sythesis. Sice Terary logic sythesis provides a ewfagled era at preset, the ecessity for the terary olie testig is a challegig itetio for today s research. D R E F Feyma Gate Feyma Gate (b) TR 2 lock Feyma Gate U V W S Figure 2:Two Reversible Olie Testable locks [9, 10] I the literature, terary testable circuits are foud i [9-10], where the authors of [9] proposed two gates (TR1 ad TR2), which are arraged i cascadig fashio to costruct Testable Terary Reversible lock (TR). TR1 is used to geerate ay terary expressio, while TR2 cotais testability features. These two gates are used to build terary expressio ad the the outputs from TR1 ad TR2 are provided ito a rail checker circuit to check the etire circuit. I [10], the modified TR1 of [9] is sketched where the gate cost for costructio of TR1 is reduced from 92 MS gate to 49 MS gate. The proposed circuit is able to detect sigle bit error oly where multiple bits failure may be occur i reversible circuits. Moreover, o geeralized methods are itroduced i [9, x0 y0 x1 y1 0 0 E1 +1 E2 +1 X3 X4 IJST 2012 IJST Publicatios UK. ll rights reserved. 198

3 Figure 3: Two pair rail checker [9, 10] Defiitio 3: Terary Galois Field Logic (TGF) [11] cosists of the set of elemets T = {0, 1, 2} ad two basic biary operatios additio (deoted by +) ad multiplicatio (deoted by or absece of ay operator). These two operatios are show i Table 1. Table 1: Terary Galois Field (GF3) operatios (a)dditio (b) Multiplicatio Z P = Figure 4: Symbol of terary M-S gate Defiitio 5: Terary Feyma Gate, couterpart of the iary Feyma gate, is show i Figure 3(a) where the outputs of the gate are Y 1 = X 1 ad Y 2 = X 1 X 2. Whe X 1 = 0, oe of the cotrollig values of the M S gates will be 2 ad o trasformatio will be applied o X 2. Therefore, Y 2 will be 0 X 2 = X 1 X 2. If X 1 = 1, the the cotrollig value of oly the secod M S gate will be 2 ad Y 2 will be X 2 1 = X 1 X 2. If X 1 = 2, the the cotrollig value of oly the first M S gate will be 2 ad Y 2 will be X 2 2 = X 1 X 2. The cost of terary Feyma gate implemetatio is show i Figure 5(a) ad the copy operatio [10] is show i Figure 5(b) [12]. Q= Z trasform of if =2 values are 2, the Z trasform is applied o the cotrolled iput, otherwise the cotrolled iput is passed uchaged. That is, the outputs of the gate are Y 1 = X 1, Y 2 = X 2, ad Y 3 = Z trasform of X 3 if X 1 = 2 ^ X 2 = 2, where Z {+1, +2, 12, 01, 02}; Y 3 = X 3 otherwise. 3-Iput Toffoli gate ca be act as multiplier by settig third iput as a 0 as give i Figure 6(b). X1 X2 X3 2 2 Z (a) Y1 Y2 Y3 X 1 X 2 Y 1 Y Z (b) Figure 6. (a) Terary Toffoli Gate (b) Toffoli gate as a multiplier Defiitio 7: Garbage Output idicates the output that is ot used as iput to other gate or as a primary output. The uutilized outputs from a gate are called garbage. Heavy price is paid off for every garbage output. Figure 7 shows the garbage output produced i Feyma gate if we wat to produce Exclusive OR operatio. Oe extra output should be produced to make the circuit reversible ad that uwated output (P=, marked as *) is kow as garbage. FG P=* Q= Figure 7: The garbage output * efore goig to the details of our desig we have discussed some recet related work o olie testig i this sectio. I the literature we have foud oly [9, 10] that icorporates o terary testig. esides literature review, some cost effective terary gate that we used i our desig are discussed. Y 3 (a) 0 (b) 3. ONLINE TESTLE REVERSILE TERNRY CIRCUIT: THE PROPOSED DESIGN Figure 5: (a) Feyma Gate (b) Copy operatio i Feyma Gate Defiitio 6: 3-qutrit Terary Toffoli Gate is show i Figure 6(a), where X 1 ad X 2 are two cotrollig iputs ad X 3 is the cotrolled iput. If the two cotrollig iput This sectio itroduces the proposed desig for olie testability of reversible terary circuits. We preset a testable block that is able to test ay terary expressio i olie. The proposed Terary Testable lock (T 3 ) is implemeted usig terary reversible gates, which evetually make the etire circuit reversible. The block, IJST 2012 IJST Publicatios UK. ll rights reserved. 199

4 show i Figure 8, is desiged very itelligetly so that the output will be 1 if the circuit works correctly. w w w +2 1 Figure 8: M-S gate with same iput O the way to desig the T 3, we have applied some GF3 [11] operatios o each testable miterm i the expressio. The required logic operatio is illustrated i Table 2. The circuit tests each miterm ad the result of the testig propagates to the ext miterm checkig block. The block is desiged i such a way that if every miterm is correct ad the etire expressio is accurate the fial testable block must produce 1. Table 2: Logic behid the proposed T 3 x y = x x.y w=x.y *x deotes a miterm (such as ab) Figure 9: Terary Testable lock Now, we are goig to develop the etire testable circuit for arbitrary terary ESOP expressios. Lets cosider a terary expressio x = ab cd which should be geerated first. While geeratig x, verificatio should also be performed over the ewly created circuit. We eed three T3 to verify ( ab cd ), two for the miters ab ad cd, ad the other oe for or geeratig ab cd.the first miterm ab ca geerate through Toffoli gate by settig third iput 0. The Feyma gate is used to geerate the duplicate of ab. Oe copies of ab is put i to the testable block for evaluatio. other copy is placed i to the Feyma gate for producig Exclusive OR with cd. The testable block for ab performs the logic operatio o the ab as described i the previous sectio. The T 3 produces 1 for ab if all operatios are acceptable. The same operatio performs o cd ad the T3 also produces 1 for cd. The 1 resultig from testable block for ab participates Sice we examie terary logic, the value of the miterm must be i 0, 1 or 2. I the testable block, 1 is added with each miterm by applyig z trasform o it, which results (miterm +1). The we perform (miterm) * (miterm +1), where the result is either 0 or 2. The w is produced by applyig z trasform o the produced result. The value of w is limited to 1or 2. The produced resultat (w) is applied o both iput of the M-S gate, as show i Figure 8. The the output of the M-S gate must be 1, if all the operatios are performed correctly. The producig 1 propagates to the ext miterm checkig block. This testable block multiplies produced 1 with aother 1 gettig as a iput from the previous block. Gate level diagram of the Reversible Terary Olie Testable Fuctio is show i Figure 9, whereas, block level oe is show Figure 10. Figure 10: Terary Testable lock (gates are represeted as block) IJST 2012 IJST Publicatios UK. ll rights reserved. 200

5 as a iput i the testable for cd. The copy of ab ad cd are put ito the Feyma gate for producig ab cd. The result is also copied by Feyma gate ad oe replica is act as a output ad aother is placed o the testable block for verifyig. This T3 produces 1 for checkig ab cd ad gettig aother 1 from previous the testable block. Their multiplicatio geerates 1. Testable circuit is show i Figure 11 ad hece, the geeralized architecture for ay arbitrary terary ESOP fuctio is show i Figure EVLUTION OF THE PROPOSED LOCK To evaluate the proposed block we have calculated both garbage ad gate cost. The followig theorems for cost calculatio ca be applicable for ay terary expressio. Theorem 1: Let be the umber of miterm i a terary expressio, g i be the garbage produced for i th miterm, where 1 i, l ad T deotes the umber of literals ad Toffoli expressio, the the total umber of garbage T G produced i the T 3 T G = g i (l-T-1) i = 1 Proof: Suppose, for i th miterm, g i garbage is geerated. If there are k literals i the miterm, the accordig to the desig g i (=k) garbage output is produced. Next we calculate garbage for miterm checkig. The T 3 is 8* 8 blocks where 1 is the actual output ad rest of the 7 are garbage output. ccordig to the proposed desig, each block produces 7 garbage outputs, ad hece the total umber of garbage produced for geeratio ad verificatio (for each miterm) is (g i +7). For Ex-or i= 1 operatios, 2 iput Feyma gate is required, which geerates 1 garbage output oly. other Feyma gate is ecessary for copyig the output. Oe output acts as a result ad other oe is placed i T 3 for observatio. Thus, 8 garbage outputs are produced i x-or. To produce x-or operatio of 2 miterms, 8*(2-1) garbage is formed, that is, for miterms, 8(-1) garbage outputs are produces for x-or operatio. Thus the umber of garbage outputs required to Terary Olie Testable lock is for miterm: i = 1 ( g i + 7) + 8(-1) = = = = i 1 i 1 g i g i For x-or operatio betwee two literals, 8(2-1) garbage output is produced. So for l literals umber of produced garbage is 8(l-1). Moreover, garbage output for ExOR operatio betwee all miterms ad all literals is 8. To miimize the gate cost we ca use 1 Toffoli gate for expressio like T= miterm x-or literal. Istead we calculate 2 gates (Toffoli ad Feyma) for the same expressio. y usig 1 Toffoli gate the umber of garbage is also reduced, so we eed to subtract 8T from the garbage cost. Thus total umber garbage produced i total is i = 1 = g i (l-1)+8-8T i = 1 g i (l-T-1). Example 4.1 Lets cosider the terary expressio abc def ghi. The testable circuit is show i Figure 13. The miterm abc is produced by 4- iput Toffoli gate. Sice there are 3 literals i each miterm the g i =3 is created for each miterm. To validate the replica of abc is placed i T 3 where 7 garbage is produced. Thus total 3+7=10 garbage is produced for miterm abc geeratio ad validatio. There are 3 miterms i the expressio so the cost for miterm is 3* 10=30. Next, abc def is geerated with 1+7 (1 for Ex-OR ad 7 for testig). The ghi is x-ored with the previous result ad agai the garbage is (1+7=8).The total garbage is =46. ccordig to Theorem 1, =3, k=3, l=0 ad T=0 so the total umbers of garbage outputs are: 3 1 g 3 +15*3 8 [where g i = 3 garbage] = =3* =46 which coforms the umber of garbage outputs i Figure 13. IJST 2012 IJST Publicatios UK. ll rights reserved. 201

6 Figure 11: Geeratio of ab cd with testable block Figure 12: rchitecture of Testable Circuit for ay arbitrary Terary ESOP fuctios Figure 13: Testable Circuit rchitecture of abc def ghi IJST 2012 IJST Publicatios UK. ll rights reserved. 202

7 Theorem 2: Let be the umber of miterm, l idicates the umber of literal, T deotes the umber of Toffoli expressio. If N G is the total umber of gates required to geeratio terary expressio the N G =9{(l+2)-(T+1)} Proof: To perform x-or operatio ad verificatio of 2 literals 9 gates are required. (1 Feyma gate for x-or oe for copy ad 7 gates i T 3 ). Thus for l literals 9(l-1) gates are eeded. To geerate ad verify each miterm we require 9 = (2+7) gates. (2 for geeratio ad 7 for testig) Thus 9 gates are iteded for miterm. For Ex-OR operatio ad verificatio betwee 2 miterms 9 gates are required. For 3 miterm 9*(3-1) gates are required ad thus for miterm 9*(-1)gates are ideted for Ex-OR operatio. So, the total required gates for miterm =9+ 9*(-1)= 9=18-9. For performig Ex-OR with literals ad miterm we eed aother 9 gates. (like a b cds). To miimize the gate cost we ca use 1 Toffoli gate for expressio like T= miterm x-or literal. Istead we calculate 2 gates (Toffoli ad Feyma) for the same expressio which requires 18T gates. y usig 1 Toffoli gate the gates cost is 9T so we subtract extra 9T from the total umber of gates. Hece, the total umber of required gates is: N G = 9(l 1) T = 9l T = 9l T = 9 {(l+2)-(t+1)} Example 4.2: Let s cosider the Terary expressio abc def ghi. We eed 9 gates for abc geeratio ad for verificatio. So, umber of gates for 3 miterm geeratio ad verifyig is 3*9=27. Next we calculate the umber of gates required for Ex-OR operatio. The requiremet is 9*(3-1) =18 ad hece, the fial value becomes: N G =27+18=45. Table 3 shows that, the compariso betwee the existig testable with that of proposed circuit i terms of gate cost. The umber of gates required to realize the bechmark fuctios are reasoably less tha the required umber of gates i the exitig method [10]. Though the garbage outputs are little bit higher for the proposed method, more research of the combiatio of coectios amog the gates ca sigificatly reduce the total garbage outputs from the desiged circuits, ad we are workig towards achievig the goal. Table 3: Gate ad Garbage cout o Proposed Desig for various echmark Circuits Terary echmark Circuit Iputs Outputs Gate Cost [10] Gate Cost [Proposed] XOR Mod sym We are also workig o the realizatio of larger circuit as the proposed algorithm shows excellet performace for small ad medium sized bechmark circuits. The compariso betwee the existig ad proposed oe, i terms of umber of gate is show i a chart (Figure 14), to illustrate the cosistecy of the proposed method. Gate Cost [10] Gate Cost (Proposed) ccordig to the theorem =3, sice there are o literals so l=0 ad also T=0. So total umber of required gates N G = 9l T= 9*0 + 18*3 9-9*0 = 54-9=45 5. EXPERIMENTL RESULTS Our proposed desig for realizatio ad testig of terary expressio have bee writte usig laguage C ad tested extesively o widows workstatio. Several experimetal results for some of the bechmark circuits are give below i Table 3 usig a Itel Petium II Desktop CPU 300 MHz uder Microsoft Widows 98 editio with 128 M RM. Durig the executio it was esured that o other applicatio is ruig. Figure 14: Compariso betwee Existig ad proposed method i terms of Gate Cost 6. CONCLUSIONS I this paper we itroduce a ew cocept o Terary Reversible Olie Testable Circuit. We have successfully IJST 2012 IJST Publicatios UK. ll rights reserved. 203

8 developed the terary testable block for olie testig which is tested with various expressios. The proposed testable block is desiged i such a way that it ca be used to test ay olie terary circuit. The theoretical uderpiigs for the proposed method are also established by various Theorems. Experimetal observatio shows that the proposed circuit obtais better result i terms of gate cost for bechmark terary expressio. REFERENCES [1] eett. C. H. 1973, Logical Reversibility of Computatio, IM J. Research ad Developmet, pp [2] Ladauer. R. 1961, Irreversibility ad Heat Geeratio i the Computig Process, IM J. Research ad Developmet, vol. 3, pp [3] Vasudeva. D.P., Lala. P.K. ad Parkerso. J.P. 2004, Olie Testable Reversible Logic Circuit Desig usig NND locks, Proc, Symposium o Defect ad Fault Tolerace, pp [4] Tara. N., ad Chowdhury.. R., Desig ad alysis of Error Detectio Module for Reversible O-Lie Testable Circuits, Silver Jubilee Coferece o Commuicatios ad VLSI Desig Vellore Istitute of Techology (VIT), Vellore, Idia, Oct 8-10, 2009, pp [5] Mitra. S. M., Hossai. M. F., war. S., ad Chowdhury..R., Olie Testable Fault Tolerat Full dder i Reversible Logic Sythesis, Secod Iteratioal Coferece o Sigals, Systems & utomatio (ICSS-11), pp , Jauary 24-25, 2011, Gujarat, Idia. [6] Mitra. S. M., Sultaa. T., war. S., ad Chowdhury.. R, Efficiet pproach to desig Reversible Fault Tolerat Cyclic Redudacy Check Circuit, Secod Iteratioal Coferece o Sigals, Systems & utomatio (ICSS-11), pp , Jauary 24-25, 2011, Gujarat, Idia. [7] Mitra. S. M., war. S., ad Chowdhury., Efficiet Desig of Check Circuit to detect Multiple Cell Errors i Reversible Logic Sythesis, Secod Iteratioal Coferece o Sigals, Systems & utomatio (ICSS-11), pp , Jauary 24-25, 2011, Gujarat, Idia. [8] Vasudeva. D.P., Lala. P.K. ad Parkerso. J.P., Novel pproach for O-lie Testable Reversible Logic Circuit Desig, Proc. of the 13th sia Test Symposium, [9] M. R. Rahma ad J.E. Rice, Olie Testable Terary Reversible Circuit. I the Proceedigs of the Reed-Muller Workshop May 25-26, 2011, Tuusula, Filad. [10] M. R. Rahma ad J.E. Rice, O Desigig a Terary Reversible Circuit for Olie Testability, IEEE Pacific Rim Coferece o Commuicatios, Computers ad Sigal Processig, Victoria, ugust 2011, pp [11] Nower. N. ad Chowdhury. R., O the Realizatio of Reversible Terary Systolic rray, Silver Jubilee Coferece o Commuicatios ad VLSI Desig Vellore Istitute of Techology (VIT), Vellore, Idia, Oct 8-10, 2009, pp [12] Muthukrisha.., Stroud. C. R., 2000, Multivalued logic gates for quatum computatio, Phys. Rev. 62(5) /1-8. [13] Chowdhury.. R.., Nazmul. R., abu. H. M. H., New pproach to Sythesize Multiple-Output Fuctios Usig Reversible Programmable Logic rray, IEEE, 19 th Iteratioal Coferece o VLSI Desig, Hyderabad, Idia, 3-7 Jauary 2006, pp IJST 2012 IJST Publicatios UK. ll rights reserved. 204