EE260: Digital Design, Spring n MUX Gate n Rudimentary functions n Binary Decoders. n Binary Encoders n Priority Encoders

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1 EE260: Digital Desig, Sprig 2018 EE 260: Itroductio to Digital Desig MUXs, Ecoders, Decoders Yao Zheg Departmet of Electrical Egieerig Uiversity of Hawaiʻi at Māoa Overview of Ecoder ad Decoder MUX Gate Rudimetary fuctios Biary Decoders Expasio Circuit implemetatio Biary Ecoders Priority Ecoders Multiplexer Multiplexer (cot.) Selects biary iformatio from oe of may iput lies ad directs it to a sigle output lie. Also kow as the selector circuit, Selectio is cotrolled by a particular set of iputs lies whose # depeds o the # of the data iput lies. For a 2 -to-1 multiplexer, there are 2 data iput lies ad selectio lies whose bit combiatio determies which iput is selected. 2-to-1-Lie Multiplexer Example: 4-to-1 MUX usig Cell Library Based Desig Sice 2 = 2 1, = 1 The sigle selectio variable S has two values: S = 0 selects iput I 0 S = 1 selects iput I 1 The equatio: Y = S I 0 + SI 1 The circuit: Decoder Eablig Circuits S I 0 I 1 Y Chapter 6, 7: MUXs, Ecoders, Decoders 1

2 EE260: Digital Desig, Sprig to 1-Lie Multiplexer usig Trasmissio Gates MUX as a Uiversal Gate We ca costruct AND ad NOT gates usig 2- to-1 MUXs. Thus, 2-to-1 MUX is a uiversal gate. z = 0x + 1x = x z = x 1 x 0 + 0x 0 = x 1 x 0 Multiple Bit Selectio Util ow, we have examied sigle-bit data selected by a MUX. What if we wat to select m-bit data/words? à Combie MUX blocks i parallel with commo select ad eable sigals Example: Costruct a logic circuit that selects betwee 2 sets of 4-bit iputs (see ext slide for solutio). Example: Quad 2-to-1 MUX Uses four 4-to-1 MUXs with commo select (S) ad eable (E). Select lie chooses betwee A i s ad B i s. The selected four-wire digital sigal is set to the Y i s Eable lie turs MUX o ad off (E=1 is o). Implemetig Boolea fuctios with Multiplexers Ay Boolea fuctio of variables ca be implemeted usig a 2-1 -to-1 multiplexer. A MUX is basically a decoder with outputs ORed together, hece this is t surprisig. The SELECT sigals geerate the miterms of the fuctio. The data iputs idetify which miterms are to be combied with a OR. Example F(X,Y,Z) = X Y Z + X YZ + XYZ + XYZ = Σm(1,2,6,7) There are =3 iputs, thus we eed a 2 2 -to-1 MUX The first -1 (=2) iputs serve as the selectio lies Chapter 6, 7: MUXs, Ecoders, Decoders 2

3 EE260: Digital Desig, Sprig 2018 Efficiet Method for implemetig Boolea fuctios For a -variable fuctio (e.g., f(a,b,c,d)): Need a 2-1 lie MUX with -1 select lies. Eumerate fuctio as a truth table with cosistet orderig of variables (e.g., A,B,C,D) Attach the most sigificat -1 variables to the -1 select lies (e.g., A,B,C) Examie pairs of adjacet rows (oly the least sigificat variable differs, e.g., D=0 ad D=1). Determie whether the fuctio output for the (A,B,C,0) ad (A,B,C,1) combiatio is (0,0), (0,1), (1,0), or (1,1). Attach 0, D, D, or 1 to the data iput correspodig to (A,B,C) respectively. The Other Example Cosider F(A,B,C) = åm(1,3,5,6). We ca implemet this fuctio usig a 4-to-1 MUX as follows. The idex is ABC. Apply A ad B to the S 1 ad S 0 selectio iputs of the MUX (A is most sig, S 1 is most sig.) Eumerate fuctio i a truth table. MUX Example (cot.) Whe A=B=0, F=C Whe A=0, B=1, F=C Whe A=1, B=0, F=C Whe A=B=1, F=C A B C F MUX implemetatio of F(A,B,C) = åm(1,3,5,6) B A C C C C F A larger Example Rudimetary Fuctios Chapter 6, 7: MUXs, Ecoders, Decoders 3

4 EE260: Digital Desig, Sprig 2018 Selectio Eablig gatig? The Other Code Coverter BCD-to-Seve-Segmet Coverter Seve-segmet display: 7 LEDs (light emittig diodes), each oe cotrolled by a iput a 1 meas o, 0 meas off Display digit 3? Set a, b, c, d, g to 1 Set e, f to 0 f e d g c b BCD-to-Seve-Segmet Coverter Iput is a 4-bit BCD code à 4 iputs (w, x, y, z). Output is a 7-bit code (a,b,c,d,e,f,g) that allows for the decimal equivalet to be displayed. a Example: Iput: 0000 BCD f g b Output: (a=b=c=d=e=f=1, g=0) e c d BCD-to-Seve-Segmet (cot.) Truth Table Digit wxyz abcdefg X X0?? Digit wxyz abcdefg X XXXXXXX 1011 XXXXXXX 1100 XXXXXXX 1101 XXXXXXX 1110 XXXXXXX 1111 XXXXXXX Decoders A combiatioal circuit that coverts biary iformatio from coded iputs to a maximum 2 coded outputs à -to- 2 decoder -to-m decoder, m 2 Examples: BCD-to-7-segmet decoder, where =4 ad m=10 Chapter 6, 7: MUXs, Ecoders, Decoders 4

5 EE260: Digital Desig, Sprig 2018 Decoders (cot.) 1-2 Decoder 2-to-4 Decoder 2-to-4 Active Low Decoder 3-to-8 Decoder 3-to-8 Decoder (cot.) address data Three iputs, A 0, A 1, A 2, are decoded ito eight outputs, D 0 through D 7 Each output D i represets oe of the miterms of the 3 iput variables. D i = 1 whe the biary umber A 2 A 1 A 0 = i Shorthad: D i = m i The output variables are mutually exclusive; exactly oe output has the value 1 at ay time, ad the other seve are 0. Chapter 6, 7: MUXs, Ecoders, Decoders 5

6 EE260: Digital Desig, Sprig 2018 Decoder Expasio Decoder with eable Implemetig Boolea fuctios usig decoders Ay combiatioal circuit ca be costructed usig decoders ad OR gates! Why? Here is a example: Implemet a full adder circuit with a decoder ad two OR gates. Recall full adder equatios, ad let X, Y, ad Z be the iputs: S(X,Y,Z) = X+Y+Z = Sm(1,2,4,7) C (X,Y,Z) = Sm(3, 5, 6, 7). Sice there are 3 iputs ad a total of 8 miterms, we eed a 3-to-8 decoder. Implemetig a Biary Adder Usig a Decoder S(X,Y,Z) = SUM m(1,2,4,7) C(X,Y,Z) = SUM m(3,5,6,7) Ecoders Ecoders (cot.) A ecoder is a digital circuit that performs the iverse operatio of a decoder. A ecoder has 2 iput lies ad output lies. The output lies geerate the biary equivalet to the iput lie whose value is 1. Chapter 6, 7: MUXs, Ecoders, Decoders 6

7 EE260: Digital Desig, Sprig 2018 Ecoder Example Example: 8-to-3 biary ecoder (octal-to-biary) Ecoder Example (cot.) A 0 = D 1 + D 3 + D 5 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 2 = D 4 + D 5 + D 6 + D 7 Ecoder Desig Issues There are two ambiguities associated with the desig of a simple ecoder: 1. Oly oe iput ca be active at ay give time. If two iputs are active simultaeously, the output produces a udefied combiatio (for example, if D 3 ad D 6 are 1 simultaeously, the output of the ecoder will be A output with all 0's ca be geerated whe all the iputs are 0's,or whe D 0 is equal to 1. Priority Ecoders Solves the ambiguities metioed above. Multiple asserted iputs are allowed; oe has priority over all others. Separate idicatio of o asserted iputs. Example: 4-to-2 Priority Ecoder Truth Table 4-to-2 Priority Ecoder (cot.) The operatio of the priority ecoder is such that: If two or more iputs are equal to 1 at the same time, the iput i the highestumbered positio will take precedece. A valid output idicator, desigated by V, is set to 1 oly whe oe or more iputs are equal to 1. V = D 3 + D 2 + D 1 + D 0 by ispectio. Chapter 6, 7: MUXs, Ecoders, Decoders 7

8 EE260: Digital Desig, Sprig 2018 Example: 4-to-2 Priority Ecoder K-Maps Example: 4-to-2 Priority Ecoder Logic Diagram 8-to-3 Priority Ecoder Uses of priority ecoders (cot.) Lik Betwee Multiplexer ad Decoder Note the regios of the multiplexer 1-to-2-lie Decoder 2 Eablig circuits 2-iput OR gate I geeral, for a 2 -to-1-lie multiplexer: -to-2 -lie decoder 2 AND gates S Decoder I 0 I 1 Eablig Circuits Y Summary of MUXs, Ecoders, Decoders MUX Gate Rudimetary fuctios Biary Decoders Expasio Circuit implemetatio Biary Ecoders Priority Ecoders Chapter 6, 7: MUXs, Ecoders, Decoders 8