Arithmetic Circuits. (Part I) Randy H. Katz University of California, Berkeley. Spring Time vs. Space Trade-offs. Arithmetic Logic Units

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1 rithmetic rcuits (art I) Rady H. Katz Uiversity of Califoria, erkeley otivatio rithmetic circuits are excellet examples of comb. logic desig Time vs. pace Trade-offs Doig thigs fast requires more logic ad thus more space Example: carry lookahead logic rithmetic Logic Uits Critical compoet of processor datapath Ier-most "loop" of most computer istructios prig Lecture #: rithmetic rcuits- Lecture #: rithmetic rcuits- Overview iary Number Represetatio ig & agitude, Oes Complemet, Twos Complemet iary dditio Full dder Revisted LU Desig CD rcuits Combiatioal ultiplier rcuit Desig Case tudy: it ultiplier equetial ultiplier rcuit Number ystems Represetatio of Negative Numbers Represetatio of positive umbers same i most systems ajor differeces are i how egative umbers are represeted Three major schemes: sig ad magitude oes complemet twos complemet ssumptios: we'll assume a bit machie word 6 differet values ca be represeted roughly half are positive, half are egative Lecture #: rithmetic rcuits Lecture #: rithmetic rcuits- Number ystems ig ad agitude Represetatio = = - High order bit is sig: = positive (or zero), = egative Three low order bits is the magitude: () thru () Number rage for bits = /- - - Represetatios for - Lecture #: rithmetic rcuits Number ystems ig ad agitude Cumbersome additio/subtractio ust compare magitudes to determie sig of result Oes Complemet N is positive umber, the N is its egative 's complemet N = ( - ) - N Example: 's complemet of hortcut method: simply compute bit wise complemet -> = - = - = = - i 's comp. Lecture #: rithmetic rcuits-6

2 Number ystems Oes Complemet Number Represetatios Twos Complemet = = - - like 's comp except shifted oe positio clockwise = = - - ubtractio implemeted by additio & 's complemet Oly oe represetatio for till two represetatios of! This causes some problems Oe more egative umber tha positive umber ome complexities i additio Lecture #: rithmetic rcuits- Lecture #: rithmetic rcuits Number ystems Twos Complemet Numbers N* = - N Example: Twos complemet of = sub = = repr. of - Number Represetatios dditio ad ubtractio of Numbers ig ad agitude result sig bit is the same as the operads' sig - () - Example: Twos complemet of - = sub hortcut method: Twos complemet = bitwise complemet - = = repr. of whe sigs differ, operatio is subtract, sig of result depeds o sig of umber with the larger magitude > -> (represetatio of -) -> -> (represetatio of ) Lecture #: rithmetic rcuits- Lecture #: rithmetic rcuits- Number ystems dditio ad ubtractio of Numbers Oes Complemet Calculatios Number ystems dditio ad ubtractio of iary Numbers Oes Complemet Calculatios - () - Ed aroud carry Why does ed-aroud carry work? Its equivalet to subtractig ad addig - N = N = ( - - N) = ( - N) - - (-N) = N = ( - - ) ( - N - ) = [ - - ( N)] - ( > N) N < - - Ed aroud carry - - after ed aroud carry: = - - ( N) this is the correct form for represetig -( N) i 's comp! Lecture #: rithmetic rcuits- Lecture #: rithmetic rcuits-

3 Number ystems dditio ad ubtractio of iary Numbers Twos Complemet Calculatios If carry-i to sig = carry-out the igore carry if carry-i differs from carry-out the overflow - - () impler additio scheme makes twos complemet the most commo choice for iteger umber systems withi digital systems Number ystems dditio ad ubtractio of iary Numbers Twos Complemet Calculatios Why ca the carry-out be igored? - N whe N > : * N = ( - ) N = (N - ) Igorig carry-out is just like subtractig - -N where N < or = - - (-N) = * N* = ( - ) ( - N) = - ( N) fter igorig the carry, this is just the right twos compl. represetatio for -( N)! Lecture #: rithmetic rcuits Lecture #: rithmetic rcuits- Number ystems Overflow Coditios dd two positive umbers to get a egative umber or two egative umbers to get a positive umber Number ystems Overflow Coditios 5 Overflow 5 No overflow - - Overflow No overflow 5 =! - - =! Overflow whe carry i to sig does ot equal carry out Lecture #: rithmetic rcuits Lecture #: rithmetic rcuits-6 Networks for iary dditio Half dder With twos complemet umbers, additio is sufficiet Networks for iary dditio Full dder i i um Carry i i um = i i i i = i i i i Carry = i i Cascaded ulti-bit dder C usually iterested i addig more tha two bits C C i um this motivates the eed for the full adder i Half-adder chematic Carry Lecture #: rithmetic rcuits- Lecture #: rithmetic rcuits

4 Networks for iary dditio Full dder = xor xor = = ( ) Networks for iary dditio Full dder/half dder tadard pproach: 6 ates lterative Implemetatio: 5 ates Half dder Half dder ( ) ( xor ) = Lecture #: rithmetic rcuits- Lecture #: rithmetic rcuits- Networks for iary dditio dder/ubtractor Networks for iary dditio Carry Lookahead rcuits Critical delay: the propagatio of carry from low to high order stages el el el el late @N two gate delays to compute dd/ubtract C stage C Overflow - = (-) = Lecture #: rithmetic fial sum ad carry Lecture #: rithmetic rcuits- Networks for iary dditio Carry Lookahead rcuits Critical delay: the propagatio of carry from low to high order stages, C Valid, C Valid, C Valid, C Valid Networks for iary dditio Carry eerate i = i i must geerate carry whe = = Carry ropagate i = i xor i carry i will equal carry out here worst case additio T T T T6 T T: Iputs to the adder are valid T: tage carry out (C) T: tage carry out (C) T6: tage carry out (C) T: tage carry out (C) delays to compute sum but last carry ot ready util 6 delays later Lecture #: rithmetic rcuits um ad Carry ca be reexpressed i terms of geerate/propagate: i = i xor i xor = i xor = i i i i = i i (i i) = i i (i xor i) = i i Lecture #: rithmetic rcuits-

5 Networks for iary dditio Reexpress the carry logic as follows: C = C C = C = C C = C = C C = C = C i i Networks for iary dditio Carry Lookahead Implemetatio gate delay gate delays gate delay dder with ropagate ad eerate Outputs Icreasigly complex logic Each of the carry equatios ca be implemeted i a two-level logic etwork Variables are the adder iputs ad carry i to stage! C C C C C C C C Lecture #: rithmetic rcuits Lecture #: rithmetic rcuits-6 Networks for iary dditio Cascaded Carry Lookahead C Networks for iary dditio Cascaded Carry Lookahead Carry lookahead logic geerates idividual carries sums computed much C C C 6 [5-] [5-] C -bit C C [] [] C -bit [] [-] [-] C -bit [-] [-] [-] C -bit C C C Lookahead Carry Uit C bit adders with iteral carry secod level carry lookahead uit, exteds lookahead to 6 bits roup = roup = Lecture #: rithmetic rcuits- Lecture #: rithmetic rcuits Networks for iary dditio Carry elect dder Redudat hardware to make carry calculatio go faster C C C : ux -it dder [:] -it dder [:] compute the high order sums i parallel oe additio assumes carry i = the other assumes carry i = C dder Low dder High -it dder [:] C 6 5 C rithmetic Logic Uit Desig ample LU =, Logical itwise Operatios Fuctio Fi = i Fi = ot i Fi = i xor i Fi = i xor i =, C =, rithmetic Operatios F = F = ot F = plus F = (ot ) plus =, C =, rithmetic Operatios F = plus F = (ot ) plus F = plus plus F = (ot ) plus plus Logical ad rithmetic Operatios Commet Iput i trasferred to output Complemet of i trasferred to output Compute XOR of i, i Compute XNOR of i, i Iput passed to output Complemet of passed to output um of ad um of ad complemet of Icremet Twos complemet of Icremet sum of ad mius Not all operatios appear useful, but "fall out" of iteral logic Lecture #: rithmetic rcuits- Lecture #: rithmetic rcuits

6 rithmetic Logic Uit Desig ample LU product terms! Equivalet to 5 gates Traditioal Desig pproach Truth Table & Espresso.i 6.o.ilb m s s ci ai bi.ob fi co.p e i i Fi X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Lecture #: rithmetic rcuits rithmetic Logic Uit Desig ample LU ultilevel Implemetatio.model alu.espresso.iputs m s s ci ai bi.outputs fi co.ames m ci co [] [] [5] fi \.ames m ci [] [] co \i i.ames s ai [] i.ames m s bi [].ames s bi [5] - -.ed [5] [] [] [] [] [] [] ates \Co Co [] [] Fi \Co [] [5] \Co \[] \[5] Lecture #: rithmetic rcuits rithmetic Logic Uit Desig ample LU Clever ulti-level Logic Implemetatio O i X i X X Fi ates (but are XOR) = blocks i Happes whe operatios ivolve i oly ame is true for whe = dditio happes whe = i, to Xor gates X, X =, X passes =, X passes rithmetic ode: Or gate iputs are i ad i (i xor ) Logic ode: Cascaded XORs form output from i ad i Lecture #: rithmetic rcuits rithmetic Logic Uit Desig TTL LU electio = =, rithmetic Fuctios Logic Fuctio C = F = ot F = ad F = (ot ) F = F = or F = ot F = xor F = ot F = (ot ) F = xor F = F = F = F = (ot ) F = F = F = mius F = mius F = (ot ) mius F = mius F = plus ( ot ) F = plus ( ot ) F = mius mius F = ot F = plus ( ) F = plus F = (ot ) plus ( ) F = ( ) F = F = plus F= (ot ) plus F = C = F = F = F = (ot ) F = zero F = plus ( ot ) plus F = plus ( ot ) plus F = ( ot ) plus F = mius F = ( ot ) plus F = plus ( ) plus F = (ot ) plus ( ) plus F = ( ) plus F = plus plus F = plus plus F = (ot ) plus plus F = plus Lecture #: rithmetic rcuits rithmetic Logic Uit Desig TTL LU Note that the sese of the carry i ad out are OOITE from the iput bits C F F F = C C Cz Cy Cx Fortuately, carry lookahead geerator maitais the correct sese of the sigals rithmetic Logic Uit Desig 6-bit LU with Carry Lookahead C C C C F F F = C 5 6 F F F = C 5 6 F F F = C 5 6 C F F F = C C C Cz Cy Cx Lecture #: rithmetic rcuits5 Lecture #: rithmetic rcuits6

7 Lecture Review We have covered: iary Number Represetatio positive umbers the same differece is i how egative umbers are represeted twos complemet easiest to hadle: oe represetatio for zero, slightly complicated complemetatio, simple additio iary Networks for dditios basic H, F carry lookahead logic LU Desig specificatio ad implemetatio Lecture #: rithmetic rcuits