ISSN: ISO 9001:2008 Certified International Journal of Engineering and Innovative Technology (IJEIT) Volume 2, Issue 5, November 2012

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1 Iteratioal Joural of Egieerig ad Iovative Techology (IJEIT) Pre Improved Weighted Modulo 2 +1 Desig Based O Parallel Prefix Adder Dr.V.Vidya Devi, T.Veishkumar, T.Thomas Leoid PG Head/Professor, Graduate Studet, Assistat Professor KCG College of Techology, Cheai, Aa Uiversity Abstract I this paper a ew desig is proposed improved weighted modulo 2 +1 desig (IWMD) based o parallel prefix adder. The existig all parallel prefix adder sklasky style, Ha Carlso, Kogge Stoe ad Bret Kug prefix structures are aalyzed the desiged weighed modulo 2 +1 adder based o Bret Kug. The Bret Kug required less area ad power whe compare with other parallel prefix adders. The ew desig all blocks are implemeted i TSMC 180m techology ad the results compariso betwee the all existig parallel prefix structure based dimiished -1 adder was reported.our proposed adders ca produce modulo sums withi the rage {2 +1 }. Idex Terms Improved Weighted Modulo 2 +1 Desig (IWMD), Parallel Prefix Adder, Modulo 2 +1, Bret Kug, VLSI Desig. I. INTRODUCTION The Residue umber system (RNS) is the most importat applicatio i DSP for computatio [3]. RNS based computatios ca achieve sigificat speedup over the biary-system-based computatio; they are widely used i DSP processors, FIR filters, ad commuicatio compoets. The RNS represetatio as follows Where m i is the member of the set of the co prime iteger called moduli. The dimiished oe umber system is ofte used for modulo operatio, where each of the iput ad output operat is decreased by 1(example A*=A-1) ad the value 0 is ot used or treated separately because it requires a additioal zero idicatio bit which is omitted here. The dimiished-1 eeds oly bit for modulo 2 +1 additio, leadig to smaller ad faster compoets. However, this icurs a overhead due to the traslators from/to the biary weighted system. O the other had, the weighted-1 represetatio uses ( + 1)-bit operads for computatios, avoidig the overhead of traslators, but requires larger area compared with the dimiished-1 represetatios. So the circular carry selectio scheme was used to improve the area time ad time power products ad efficietly select the correct carry-i sigals for fial modulo additio. The previous methods all deal with dimiished-1 modulo additio [2]. However, the hardware for decreasig /icreasig the iputs/outputs by 1 is omitted i the literature. I additio, the value zero is ot allowed i dimiished-1 modulo 2 +1 additio, ad hece, the zero-detectio circuit is required to avoid icorrect computatio. The Bret Kug tree based prefix structure uses oly less area whe compared with the sklasky style prefix structure [1]. This leads to icreased hardware cost. The proposed uified approach for weighted ad dimiished-1 modulo 2 +1 additio is based o makig the modulo 2 +1 additio of two ( + 1)-bit iput umbers A ad B cogruet to Y + U + 1, where Y ad U are two -bit umbers [1]. Thus, ay dimished-1 adder ca be used to perform weighted modulo 2 +1 additio of Y ad U. The author s first used the traslators to decrease the sum of two -bit iputs A ad B by 1 ad the performed the weighted modulo additio usig dimiished-1 adders [1]. I this desig the advatages of both of the previous two modulo (2 +1) adders (dimiished-1, weighted-1) are combied to reduce the area & improve the performace. Reviewig is carried out for sklasky style, Ha Carlso, Kogge Stoe ad Bret Kug prefix structure i sectio II. The proposed modulo 2 +1 additio preseted i sectio III. Our coclusios are i sectio IV. II. PARALLEL PREFIX ADDER A. Sklasky Prefix Tree The parallel prefix tree is used to compute geerate ad propagate sigals. This is ofte desirable to use a adder with good timig, area ad efficiecy tradeoff characteristics. They geerate ad propagate sigals computatio performed with adjacet blocks. The carry computatio method leads to speed up the overall operatio sigificatly. The equatio for computig the geerate ad propagate values of the combied blocks are G i,k = G i,j+1 +(P j,j+1 + G j,k ) P i,k = P i,j+1 + P j,k Fig 1: 16-Bit Sklasky Prefix Tree 277

2 Iteratioal Joural of Egieerig ad Iovative Techology (IJEIT) May parallel prefix adders are available. The parallel prefix adders are differig with i desig of carry propagatio of logic levels ad area tradeoff characteristics. A Sklasky parallel-prefix adder (Figure 1) was proposed for coditioal sum. Rather tha waitig for propagated carry sigal to geerate each sum this scheme first geerates sum ad carry-out pairs by usig both possibilities of carry-i sigal at each bit positio. The correct output is the selected upo the arrival of carry-i sigal. Ad it has a prefix structure of miimal depth ad is therefore amog the fastest adder architectures. Sklasky prefix tree use less logic levels to compute the carries. I additio, it uses less cells whe compare with Kogge-Stoe structure at the cost of higher fa-out. The above shows the 16-bit Sklasky prefix tree with critical path i solid lie. The sklasky style prefix structure uses large area whe compared with the Bret-kug tree parallel prefix structures For a 16-bit Sklasky prefix tree, the maximum fa-out is 9 (i.e. f = 3). The structure ca be viewed as a compacted versio of Bret-kug's, where logic levels are reduced ad fa-out icreased. The umber of logic levels is log2. Each logic level has =2 cells as ca be observed i Figure 4.6. The area is estimated as (/2) log2. Whe = 16, 32 cells are required. [ B. Ha Carlso Prefix Tree The Ha-Carlso adder combies the Bret-Kug ad Kogge-Stoe structures ito a hybrid structure ad it has a maximum fa-out of 2 or f = 0. This is more efficiet ad Suitable for VLSI implemetatio. Fig 3: 16 bit Kogge Stoe prefix tree D. Bret ad Kug Prefix Tree The ext parallel prefix tree is Bret Kug (Figure 4) ofte used to compute geerate ad propagate sigals which is a well-kow structure with relatively sparse etwork. The Bret Kug adder is oe of the more advaced desigs, havig a gate level depth of O (log2 ()). The fa-out is amog the miimum as f = 0. So is the wire tracks where t = 0. The cost is the extra L - 1 logic levels. Fig 2: 16 Bit Ha Carlso Prefix Tree The Ha Carlso ad Sklasky have same umber of cells but the ham Carlso (Figure 2) eeds less time compute the cells. C. Kogge Stoe Prefix Tree The ext parallel prefix tree is Kogge stoe (Figure 3) ad the Kogge stoe adder has low depth, high ode cout it implies more area ad miimal fa out of 1 at each ode it implies faster performace. [ Fig 4: 16 Bit Bret Kug prefix tree The critical path is show i the figure with a thick gray lie. Bret-Kug tree uses oly less area whe compared with Sklasky prefix tree. The Bret-Kug adder is a good balace betwee area, power cost ad performace. The Bret-Kug parallel-prefix adder gives a good trade-off betwee area ad speed, lyig i the rage of -15% to -30% area reductio at +15% to +30% delay icrease as compared to the faster Sklasky parallel Prefix adder. III. PROPOSED MODEL A. Modulo Calculatio A improved area-efficiet weighted modulo 2 +1 adder desig usig dimiished-1 adders with simple correctio 278

3 Iteratioal Joural of Egieerig ad Iovative Techology (IJEIT) schemes [1]. This is achieved by subtractig the sum of two ( + 1)-bit iput umbers by the costat ad producig carry (V) ad sum (U) vectors. I additio, we make the two iputs A ad B to be i the rage {0, 2 }. A+B = { A+B-(2 +1) 2, if (A+B) > 2 A+B-(2 +1) 2 +1, Otherwise A+B 2 +1 = { A+B-(2 +1), if (A+B) > 2 A+B, Otherwise The equatio ca be stated as A+B = { A+B-(2 +1) 2, if (A+B) > 2 A+B-(2 +1) 2 + (2 +1) 2, Otherwise Give two ( + 1)-bit iputs,. A = a a 1... a 0 ad B =b b 1,..., b 0, where 0 A, B 2. The weighted modulo 2 +1 of A + B ca be represeted as follows From this equatio the value of modulo 2 +1 additio ca be obtaied by subtractig 2 +1 from the sum of A ad B. The modulo 2 +1 additio ca the performed usig parallel prefix structure(bret-kug) dimiished-1 adders by takig i the sum(u) ad carry vectors(v) plus the iverted ed aroud carry with simple correctio schemes.. For Geeratio v -1, u -1, ad fix (*: coditios whe v-1 = 2) Fig 5: Geeral Block Diagram Of Modulo 2 +1 Table 1 Truth Table [1] a b a -1 b -1 u -1 v -1 FIX * 1 0 1* 1 1 1* 1 The V -1,U -1 ad FIX which is produced by truth table. Where is X deoted as do t care. The FIX is wired OR with the carry out of sum of carry (V) ad sum (U) to be the iverted ed aroud carry as a carry i for dimiished -1 additio. I the geeral block diagram of 2 +1 adder the iverter has bee take as cout as a iput. I this ed-aroud adder, cout eeds to be iverted before goig to the icremeted. Fig 6: Block Diagram Of Proposed Modulo 2 +1 Adder The modified block diagram for modulo 2 +1 additio is give above. Two most sigificat bit take as a iput to the correctio scheme. The correctio scheme output wired OR with cout, which is the iput of ed aroud block. These all blocks are implemeted i 0.13 µm CMOS techology ad the results compariso betwee the Sklasky ad Bret Kug parallel prefix structure based dimiished -1 adder give below. 279

4 Iteratioal Joural of Egieerig ad Iovative Techology (IJEIT) IV. SYNTHESIZE RESULT AND COMPARISON WITH TSMC 180 NM TECHNOLOGY V. CONCLUSION I coclusio, we have implemeted improved weighted modulo 2 +1 desig based o parallel prefix adder. I this paper the Bret Kug parallel prefix structure based dimiished -1 adder to achieve better area ad power tradeoff charactreistics i TSMC 180 m techology. This will produce sums that are withi the rage {0,2 }. Fig 7: 16 Bit Sklasky Area with TSMC 180 Nm Fig 8: 16 Bit Kogge Stoe Area with TSMC 180 Nm Fig 9: 16 Bit Ha Carlso Area with TSMC 180 Nm Fig 10: 16 Bit Bret ad Kug Area with TSMC 180 Nm Table 2. POWER AND AREA SYNTHESIS RESULT FOR VARIOUS MODULO 2 N +1 ADDERS Adder 16 bit Power(mw) Area(µm) Sklasky Kogge Stoe Ha Carlso Bret Kug REFERENCES [1] Tso-Big Juag, Chi-Chieh Chiu ad Mog- Yu Tsai, Improved Area Efficiet Weighted Modulo 2+1 Adder Desig With Simple Correctio Schemes Vol, 57.No. 3. Mar [2] H.T.Vergos ad C.Efstathiou, A uifyig approach for weighted ad dimiished-1 modulo 2+1 additio IEEE Tras.circuit system 0ct [3] M.A.soderstrad, W.K.Jekis, Residue Number System Arithmetic Moder applicatio i Digital Sigal Processig. [4] F. Liu, Q. Ta Field programmable gate array prototypig of ed-aroud carry parallel prefix tree architectures IET Computers & Digital Techiques Received o 27th March [5] J.Sklasky, coditioal sum additio logic IRE Tras. Electro comput Jue [6] Amir Sabbagh Molahosseii, Keiva Navi, Chitra Dadkhah, Omid Kavehei, ad Somayeh Timarchi. Efficiet Reverse Coverter Desigs for the New 4-Moduli Sets IEEE trasactios o circuits ad systems, april [7] Feg Liu, Fariborz F.F, Otmae Ait Mohamed A Comparative Study of Parallel Prefix Adders i FPGA Implemetatio of EAC th Euro micro Coferece o Digital System Desig. [8] Somayeh Timarchi, Keiva Navi Improved Modulo 2 +1 Adder Desig Iteratioal Joural of Computer ad Iformatio Egieerig 2: ] L. M. Leibowitz, A Simplified Biary Arithmetic for the Fermat Number Trasform, IEEE Tras. Acoustics, Speech, Sigal Processig, vol. 24, pp , [9] H.T. Vergos, et al., Dimiished-1 modulo 2+1 Adder Desig, IEEE Tras. Computers, vol. 51, pp , [10] R. Zimmerma, Efficiet VLSI Implemetatio of Modulo (2±1) Additio ad Multiplicatio, Proc. 14th IEEE Symp. Computer Arithmetic, pp , Apr [11] S. Timarchi, O. Kavehei, ad K. Navi, Low Power Modulo 2+1 Adder Based o Carry Save Dimiished-1 Number System, America Joural of Applied Scieces 5 (4), pp , [12] S. Timarchi ad K. Navi, A Novel modulo 2+1 Adder Scheme, 12 th Iteratioal CSI Computer Coferece, Feb [13] S. Timarchi, K. Navi, ad M. Hosseizade, New Desig of RNS Subtractor for modulo 2+1, 2d IEEE Iteratioal Coferece o Iformatio & Commuicatio Techologies: From Theory to Applicatio, Apr

5 Iteratioal Joural of Egieerig ad Iovative Techology (IJEIT) [14] B. Parhami, RNS Represetatio with Redudat Residues, Proc. Of the 35th Asilomar Cof. o Sigals, Systems, ad Computers, Pacific Grove, CA, pp , 4-7 Nov [15] S. Timarchi, K. Navi, ad M. Hosseizade, New Desig of RNS Subtractor for modulo 2+1, 2d IEEE Iteratioal Coferece o Iformatio & Commuicatio Techologies: From Theory to Applicatio, Apr [16] B. Parhami, RNS Represetatio with Redudat Residues, Proc. Of the 35th Asilomar Cof. o Sigals, Systems, ad Computers, Pacific Grove, CA, pp , 4-7 Nov AUTHOR BIOGRAPHY Dr.V.Vidya devi got her PHd i Electroics ad commuicatio, egieerig doe her PG from Aa uiversity ad graduated from Aa uiversity Guidy campus i 1986.Presetly she is workig as a PG coordiator / Professor i K C G college of techology. Her areas of iterest are digital sigal processig, etwork security ad VLSI desig. Mr. T.Veishkumar Got his PG degree from K C G College of techology ad at preset workig as a assistat Lecturer i Aai Aruai egieerig college, Tamil Nadu. His area of iterest is i embedded system ad VLSI desig techology Mr.TThomas Leoid post graduated from Bharath uiversity.presetly workig as a Assistat professor i K C G college of techology, Cheai. He is guidig the studets i embedded system ad VLSI techology.his area of iterest are VLSI testig ad optimum performace i power ad area reductio i VLSI Desig.. 281