Introduction to Distributed Arithmetic. K. Sridharan, IIT Madras

Transcription

1 Itroductio to Distriuted rithmetic. Sridhara, IIT Madras

2 Distriuted rithmetic (D) efficiet techique for calculatio of ier product or multipl ad accumulate (MC) The MC operatio is commo i Digital Sigal Processig lgorithms

3 What is the direct method of implemetig ier products or MC? The direct method ivolves usig dedicated multipliers Multipliers are fast ut the cosume cosiderale hardware

4 Illustratio of MC Operatio The followig expressio represets a multipl ad accumulate operatio x x x i. e. umerical example 3,4,45,3 x 4,0,,67 ( x 4) 78 ( )

5 How does distriuted arithmetic wor? Distriuted rithmetic (D) is a techique that is itserial i ature. It ca therefore appear to e slow It turs out that whe the umer of elemets i a vector is earl the same as the wordsize, D is quite fast D `replaces the explicit multiplicatios ROM loo-ups a efficiet techique to implemet o Field Programmale Gate rras (FPGs)

6 What does D achieve? I D, multiplicatios are reordered ad mixed such that the arithmetic ecomes distriuted through the structure rather tha eig lumped rea savigs from usig D ca e up to 80% i DSP hardware desigs While distriuted arithmetic techique itself has ee aroud for more tha 30 ears (Peled ad iu, 974), iterest i this has ee revived the use of Field Programmale Gate rras (FPGs) for DSP Whe D is implemeted i FPGs, oe ca tae advatage of memor i FPGs to implemet the MC operatio

7 The Formulatio for D Cosider a. et x e a -it scaled two s complemet umer. I other words, where 0 x < x : { 0,,, (-) } is the sig it x. We ca express x as c. Sustitutig () i (), x 0 0 () ( ) ( ) () 0 (3)

8 Cotiuig the D formulatio ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) M ( ) ( ) 0 ( ) ( ) ( ) ( ) ) ( ) ( 0 (3) Expadig this part

9 Further simplificatio leads to ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) M ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) M

10 The rewrite showig iterchage of sum.. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) M 0 ) ( 0 ) ( (4)

11 How is the hardware realizatio? Cosider the equatio (4) rewritte as: ( 0 ) has ol possile values ( 0 ) has ol possile values With the sig it as a iput, we ca store it i a ROM of size*

12 Example et umer of taps e 4 The fixed coefficiets are 0.7, -0.3, , 4 0. ( 0 ) (4) We eed 4 6-words ROM

13 ROM: ddress ad Cotets Cotets

14 Plus ad Mius Poits The architecture has accomplished MC without a explicit multiplier The size of ROM, however,grows expoetiall with each added iput address lie For each elemet i a vector, we have a address lie. So we ll have address lies If is 6, this implies 6 ( i.e., 64) of ROM

15 Offset iar codig to reduce ROM size x [ x ( x )] x x 0 ( ) 0 s-complemet x ( ) ( ) ( ) 0 0

16 Rewritig x differetl, we have x ( ) ( ) ( ) 0 0 Defie: Offset Code, { c ( ), Fiall 0 0 x c 0 where c ( ) {,}

17 Usig the ew x we have Sustitute the ew x i x c ) ( 0 0 ) ( x c ) ( 0 c ) ( 0 c (9)

18 The ew Formulatio i Offset Code ( ) c 0 If we let ( c c ) Q c c ad Q ( 0 ) Costat 0 ( ) ( ) c c Q( ) Q c 0

19 The Gai: have reduced storage to 8 rows 3 4 c c c 3 c 4 Cotets / ( 3 4 ) / ( 3-4 ) / ( ) / ( ) / ( ) / ( ) / ( ) / ( ) / (- 3 4 ) / (- 3-4 ) / ( ) / ( ) / ( ) / ( ) / ( ) / ( ) 0.74 Iverse smmetr

20 D Hardware with Offset Biar Codig x selects etwee the two smmetric halves T s idicates whe the sig it arrives

21 How to reduce ROM size further? Oe approach to reduce the ROM size is decomposig the ROM I particular, ca divide the address its of the ROM ca e divided ito (/) groups of its So a ROM of size ca e divided ito / ROMs of size Will eed a adder to add the outputs of these ROMs ad a multi-iput accumulator This is a active area of research.

22 Comparisos i iitial ears of D Traditioal comparisos are with multiplier-ased solutios for prolems pertaiig to filters Whe D was devised (i the 970s), the comparisos give were i terms of umer of TT ICs required for mechaizatio of a certai tpe of filter I particular, for a eighth order digital filter operatig at a word rate close to MHz, 7 ICs with a total power cosumptio of aout 30 W was stated with the D approach while 40 ICs with a power dissipatio of 96 W was idicated for a multiplierased solutio

23 Curret Status: D vs Mplr o FPG stud of computatio of Y ax X cx3 was performed with code developed i Verilog. Elemets were chose to have 8-it size Sparta-XC3S500E ased sthesis was carried out i Xilix ISE 0. Whe uilt-i multipliers were used, the resource cosumptio was 35 slices ad 3 multipliers. The comiatioal path dela was 5.7 s. For the D-ased solutio, 47 slices were used ad the max frequec of operatio was 4.57 MHz. Power cosumptio (otaied usig XPower) for D-ased approach was slightl less tha that for the multiplier-ased solutio

24 Refereces. Peled ad B. iu, ew hardware realizatio of digital filters, IEEE Trasactios o coustics, Speech, ad Sigal Processig, Vol. SSP-, o. 6, pp , Dec. 974 S.. White, pplicatios of distriuted arithmetic to digital sigal processig: tutorial review, IEEE SSP Magazie, Jul, 989 UR rithmetic.ppt Xilix pplicatio ote, The role of distriuted arithmetic i FPG-ased sigal processig,