Chapter 2 Modulo Addition and Subtraction

Transcription

1 Chapter 2 Modulo Additio ad Subtractio I this Chapter, the basic operatios of modulo additio ad subtractio are cosidered. Both the cases of geeral moduli ad specific moduli of the form 2 1ad2 + 1 are cosidered i detail. The case with moduli of the form ca beefit from the use of dimiished-1 arithmetic. Multi-operad modulo additio also is discussed. 2.1 Adders for Geeral Moduli The modulo additio of two operads A ad B ca be implemeted usig the architectures of Figure 2.1a ad b [1, 2]. Essetially, first A+B is computed ad the m is subtracted from the result to fid whether the result is larger tha m or ot. (Note that TC stads for two s complemet.) The usig a 2:1 multiplexer, either (A+B)or(A+B m) is selected. Thus, the computatio time is that of oe -bit additio, oe ( + 1)-bit additio ad delay of a multiplexer. O the other had, i the architecture of Figure 2.2b, both (A+B) ad (A+B m) are computed i parallel ad oe of the outputs is selected usig a 2:1 multiplexer depedig o the sig of (A + B m). Note that a carry-save adder (CSA) stage is eeded for computig (A+B m) which is followed by a carry propagate adder (CPA). Thus, the area is more tha that of Figure 2.2a, but the additio time is less. The area A ad computatio time Δ for both the techiques ca be foud for -bit operads assumig that a CPA is used as Spriger Iteratioal Publishig Switzerlad 2016 P.V. Aada Moha, Residue Number Systems, DOI / _2 9

2 10 2 Modulo Additio ad Subtractio a A Adder B b A B TC of m TC of m Adder CSA A+B 2:1 MUX Adder A+B-m A+B 2:1 MUX Adder A+B-m (A+B) mod m (A+B) mod m Figure 2.1 Modulo adder architectures: (a) sequetial (b) parallel Figure 2.2 Modular adder due to Hiasat (adapted from [6] IEEE2002) X SAC Y B A b a CPG P G p g MUX CLA for C out 1 CLAS R A cascade ¼ ð2 þ 1ÞA FA þ A 2:1MUX þ A INV, Δ cascade ¼ ð2 þ 1ÞΔ FA þ Δ 2:1MUX þ Δ INV A Parallel ¼ ð3 þ 2ÞA FA þ A 2:1MUX þ A INV, Δ parallel ¼ ð þ 2ÞΔ FA þ Δ 2:1MUX þ Δ INV ð2:1þ where Δ FA, Δ 2:1MUX, ad Δ INV are the delays ad A FA,A 2:1MUX ad A INV are the areas of a full-adder, 2:1 Multiplexer ad a iverter, respectively. O the other

3 2.1 Adders for Geeral Moduli 11 had, by usig VLSI adders with regular layout e.g. Bret Kug adder [3], the area ad delay requiremets will be as follows: A cascade ¼ 2ðlog 2 þ 1ÞA FA þ A 2:1MUX þ A INV, Δ cascade ¼ 2ðlog 2 þ 1ÞΔ FA þ Δ INV, A Parallel ¼ ð þ 1 þ log 2 þ log 2 ð þ 1Þþ2ÞA FA þ A 2:1MUX þ A INV, Δ parallel ¼ ððlog 2 þ 1Þþ2ÞΔ FA þ Δ 2:1MUX þ Δ INV ð2:2þ Subtractio is similar to the additio operatio wherei (A B) ad (A B+m) are computed sequetially or i parallel followig architectures similar to Figure 2.1a ad b. Multi-operad modulo additio has bee cosidered by several authors. Alia ad Martielli [4] have suggested the mod m additio of several operads usig a CSA tree tryig to keep the partial results at the output of each CSA stage withi the rage (0, 2 ) by addig a proper value. The three-iput additio i a CSA yields - bit sum ad carry vectors S ad C. S is always i the rage {0, 2 }. The computatio of (2C + S) m is carried out as (2C + S) m ¼ L + H +2T C + T S ¼ L + H + T + km where k > 0 is a iteger. Note that L ¼ 2(C T C ) ad H ¼ S T S were T S ¼ s ad T C ¼ c c Thus, usig s 1, c 1, c 2 bits, T ca be obtaied usig a 7:1 MUX ad added to L, H. Note that L is obtaied from C by oe bit left shift ad H is obtaied as ( 1)-bit LSB word of S. All the operads ca be added usig a CSA tree ad the fial result U F ¼ 2C F + S F is reduced usig a modular reductio uit which fids U F, U F m, U F 2 m ad U F 3 m usig two CLAs ad based o the sig bits of the last three words, oe of the aswers is selected. Elleithi ad Bayoumi [5] have preseted a θ(1) algorithm for multi-operad modulo additio which eeds a costat time of five steps. I this techique, the two operads A ad B are writte i redudat form as A 1, A 2 ad B 1, B 2, respectively. The first three are added i a CSA stage which will yield sum ad carry vectors. These two vectors temp1 ad temp2 ad B 2 are added i aother CSA which will yield sum ad carry vectors temp3 ad temp4. I the third step, to temp3 ad temp4 vectors, a correctio term (2 m) or 2(2 m) is added i aother CSA stage depedig o either oe or both carry bits of temp1 ad temp2 are 1 to result i the sum ad carry vectors temp5 ad temp6. Depedig o the carry bit, i the ext step (2 m) is added to yield fial result i carry save form as temp7 ad temp8. There will be o overflow thereafter. Hiasat [6] has described a modulo adder architecture based o a CSA ad multiplexig the carry geerate ad propagate sigals before beig drive to the carry computatio uit. I this desig, the output carry is predicted that could result from computatio of A+B+Zwhere Z ¼ 2 m. If the predicted carry is 1, a adder proceeds i computig the sum A+B+Z. Otherwise, it computes the sum A+B. Note that the calculatio of Sum ad Carry bits i case of bit z i beig 1 or 0 is quite simple as ca be see for both these cases:

4 12 2 Modulo Additio ad Subtractio s i ¼ a i b i, c iþ1 ¼ a i b i ad ^s i ¼ a i b i, ^c iþ1 ¼ a i þ b i Thus, half-adder like cells which give both the outputs are used. Note that s i, c i+1, ^s i, ^c iþ1 serve as iputs to carry propagate ad geerate uit which has outputs P i, G i, p i, g i correspodig to both the cases. Based o the computatio of c out usig a CLA, a multiplexer is used to select oe of these pairs to compute all the carries ad the fial sum. The block diagram of this adder is show i Figure 2.2 where SAC is sum ad carry uit, CPG is carry propagate geerate uit, ad CLA is carry look ahead uit for computig C out. The usig a MUX, either P, G or p, g are selected to be added usig CLA summatio uit (CLAS). The CLAS uit computes all the carries ad performs the summatio P i c i to produce the output R. This desig leads to lower area ad delay tha the desigs i Refs. [1, 5]. Adders for moduli (2 1) ad (2 + 1) have received cosiderable attetio i literature which will be cosidered ext. 2.2 Modulo (2 1) Adders Efstathiou, Nikolos ad Kalamatios [7] have described a mod (2 1) adder. I this desig, the carry that results from additio assumig carry iput is zero is take ito accout i reformulatig the equatios to compute the sum. Cosider a mod 7 adder with iputs A ad B. With the usual defiitio of geerate ad propagate sigals, it ca be easily see that for a covetioal adder we have c 0 ¼ G 0 þ P 0 c 1 c 1 ¼ G 1 þ P 1 c 0 c 2 ¼ G 2 þ P 2 G 1 þ P 2 P 1 g 0 ð2:3aþ ð2:3bþ ð2:3cþ Substitutig c 1 i (2.3a) with c 2 due to the ed-aroud carry operatio of a mod (2 1) adder, we have c 0 ¼ G 0 þ P 0 G 2 þ P 0 P 2 G 1 þ G 0 P 2 P 1 G 0 ¼ G 0 þ P 0 G 2 þ P 0 P 2 G 1 c 1 ¼ G 1 þ P 1 G 0 þ P 1 P 0 G 2 c 2 ¼ G 2 þ P 2 G 1 þ P 2 P 1 G o ð2:4þ ð2:5aþ ð2:5bþ A implemetatio of mod 7 adder with double represetatio of zero (i.e. output ¼ 7 or zero) is show i Figure 2.3a where s i ¼ P i c i 1. A simple modificatio ca be carried out as show i Figure 2.3b to realize a sigle zero. Note that the output ca be 2 1, if both the iputs are complemets of each other. Hece, this coditio ca be used by computig P ¼ P 0 P 1 P 2...P 1 ad modifyig the equatios as

5 2.2 Modulo (2 1) Adders 13 a X 0 P 0 Y 0 G 0 C-1 S 0 P 1 X 1 Y 1 G 1 C 0 S 1 X 2 P 2 Y 2 G 2 C 1 S 2 b X 0 P 0 Y 0 G 0 C-1 S 0 P 1 X 1 Y 1 G 1 X 2 P 2 C 0 S 1 Y 2 G 2 C 1 S 2 Figure 2.3 (a) Mod 7 adder with double represetatio of zero (b) with sigle represetatio of zero (adapted from [7] IEEE1994)

6 14 2 Modulo Additio ad Subtractio s i ¼ P i þ P c i 1 for 0 i 1: ð2:6þ The architectures of Figure 2.3, although they are elegat, they lack regularity. Istead of usig sigle level CLA, whe the operads are large, multiple levels ca also be used. Aother approach is to cosider the carry propagatio i biary additio as a prefix problem. Various types of parallel-prefix adders e.g. (a) Lader Fischer [8], (b) Kogge-Stoe [9], (c) Bret Kug [3] ad (d) Kowles [10] are available i literature. Amog these, type (a) requires less area but has ulimited fa out compared to type (b). But desigs based o (b) are faster. Zimmerma [11] has suggested usig a additioal level for addig ed-aroudcarry for realizig a mod (2 1) adder (see Figure 2.4a) which eeds extra hardware ad more over, this carry has a large fa out thus makig it slower. Kalampoukas et al. [12] have cosidered modulo (2 1) adders usig parallelprefix adders. The idea of carry recirculatio at each prefix level as show i Figure 2.4b has bee employed. Here, o extra level of adders will be required, thus havig miimum logic depth. I additio, the fa out requiremet of the carry output is also removed. These architectures are very fast while cosumig large area. The area ad delay requiremets of adders ca be estimated usig the uit-gate model [13]. I this model, all gates are cosidered as a uit, whereas oly exclusive- OR gate couts for two elemetary gates. The model, however, igores fa-i ad fa-out. Hece, validatio eeds to be carried out by usig static simulatios. The area ad delay requiremets of mod (2 1) adder described i [12] are 3log +4 ad 2log + 3 assumig this model. Efstathiou et al. [14] have also cosidered desig usig select-prefix blocks with the differece that the adder is divided ito several small legth adder blocks by proper itercoectio of propagate ad geerate sigals of the blocks. A selectprefix architecture for mod (2 1) adder is preseted i Figure 2.5. Note that d, f ad g idicate the word legths of the three sectios. It ca be see that c i,0 ¼ BG 2 þ BP 2 BG 1 þ BP 2 BP 1 BG 0 c i, 1 ¼ c out, 0 ¼ BG 0 þ BP 0 BG 2 þ BP 0 BP 2 BG 1 c i, 2 ¼ c out, 1 ¼ BG 1 þ BP 1 BG 0 þ BP 1 BP 0 BG 2 where BG i ad BP i are block geerate ad propagate sigals outputs of each block. Tyagi [13] has give a algorithm for selectig the legths of the various adder blocks suitably with the aim of miimizatio of adder delay. Note that desigs based o parallel-prefix adders are fastest but are more complex. O the other had, CLA-based adder architecture is area effective. Select prefix-architectures achieve delay closer to parallel prefix adders ad have complexity close to the best adders. Patel et al. [15] have suggested fast parallel-prefix architectures for modulo (2 1) additio with a sigle represetatio of zero. I these, the sum is computed with a carry i of 1. Later, a coditioal decremet operatio is

7 2.2 Modulo (2 1) Adders 15 a a -1 b -1 a -2 b -2 a 1 b 1 a0 b 0 prefix structure C i C out s -1 s -2 s 1 s 0 b b 7 a 7 b 6 a 6 b 5 a 5 b 4 a 4 b 3 a 3 b 2 a 2 b 1 a 1 b 0 a 0 C 7 C* -1 C* 6 C* 5 C* 4 C* 3 C* 2 C*1 C* 0 S 7 S 6 S 5 S 4 S 3 S 2 S 1 S 0 Figure 2.4 Modulo (2 1) adder architectures due to (a) Zimmerma ad (b) modulo (2 8 1) adder due to Kalampoukas et al. ((a) adapted from [11] IEEE1999 ad (b) adapted from [12] IEEE2000) performed. However, by cyclically feedig back the carry geerate ad carry propagate sigals at each prefix level i the adder, the authors show that sigificat improvemet i latecy is possible over existig desigs.

8 16 2 Modulo Additio ad Subtractio BG 2 BG 1 BG 0 BP 2 BP 1 BP 0 C i,2 C i,1 C i,0 BLOCK 2 Adder (d+f+g-1:f+g) BLOCK 1 Adder (f+g-1:g) BLOCK 0 Adder (g-1:0) Figure 2.5 Modulo 2 d+f+g 1 adder desig usig three blocks (adapted from [14] IEEE2003) 2.3 Modulo (2 + 1) Adders Dimiished-1 arithmetic is importat for hadlig moduli of the form 2 +1.This is because of the reaso that this modulus chael eeds oe bit more word legth tha other chaels usig moduli 2 ad 2 1. A solutio give by Liebowitz [16] is to represet the umbers still by bits oly. The dimiished-1 umber correspodig to ormal umber A i the rage 1 to 2 is represeted as d(a) ¼ A 1. If A ¼ 0, a separate chael with oe bit which is 1 is used. Aother way of represetig A i dimiished-1 arithmetic is (A z, A d ) where A z ¼ 1, A d ¼ 0 whe A ¼ 2, A z ¼ 0, A d ¼ A 1 otherwise. Due to this represetatio, some rules eed to be built to perform operatios i this arithmetic which are summarized below. Followig the above otatio, we ca derive the followig properties [17]: (a) A+B¼ C correspods to daþ ð BÞ ¼ ðda ð ÞþdB ð Þþ1Þmod ð2 þ 1Þ ð2:7þ (b) Similarly, we have da ð BÞ ¼ da ð ÞþdB ð Þ þ1 modð2 þ 1Þ ð2:8þ (c) It follows further that d X k¼1 k ¼ ðda ð 1 ÞþdA ð 2 ÞþdA ð 3 Þþ... þ da ð k Þþ 1Þ mod ð2 þ 1Þ Next, d 2 k A ¼ daþ ð A þ A þ...þ AÞ ¼ 2 k da ð Þþ2 k 1 mod ð 2 þ 1Þ: or 2 k da ð Þ ¼ ð2:9þ d 2 k A 2 k þ 1 mod ð 2 þ 1Þ ð2:10þ

9 2.3 Modulo (2 + 1) Adders 17 I order to simplify the otatio, we deote a dimiished-1 umber usig a asterisk e.g. d(a) ¼ A* ¼ A 1. Several mod (2 + 1) adders have bee proposed i literature. I the case of dimiished-1 umbers, mod (2 + 1) additio ca be formulated as [11] S 1 ¼ S* ¼ ða* þ B* þ 1Þ mod ð2 þ 1Þ ¼ ða* þ B* Þmod ð2 Þ if ða* þ B* Þ 2 ad ða* þ B* þ 1Þ otherwise ð2:11þ where A* ad B* are dimiished-1 umbers ad S ¼ A + B. The additio of 1 ca be carried out by ivertig the carry bit C out ad addig i a parallel-prefix adder with C i ¼ C out (see Figure 2.6): ða* þ B* þ 1Þmod 2 ð þ 1Þ ¼ A* þ B* þ C out mod 2 ð Þ ð2:12þ I the case of ormal umbers as well [11], we have S þ 1 ¼ ða þ B þ 1Þmod 2 ð þ 1Þ ¼ A þ B þ C out mod 2 ð Þ ð2:13þ where S ¼ A + B with the property that (S + 1) is computed. I the desig of multipliers, this techique will be useful. Note that dimiished-1 adders have a problem of correctly iterpretig the zero output sice it may represet a valid zero (additio with a result of 1) or a real zero output (additio with a result zero) [14]. Cosider the two examples of modulo Figure 2.6 Modulo ð2 þ 1Þ adder architecture for dimiished-1 arithmetic (adapted from [18] IEEE2002) b -1 b -2 b 1 b 0 a -1 a -2 a 1 a 0 Prefix Computatio G -1 G-2,P -2 c* -1 G 1,P 1 G 0,P 0 c* -2 c* -3 c* 1 c* 0 S -1 S -2 S 1 S 0

10 18 2 Modulo Additio ad Subtractio 9 additio (a) A ¼ 6 ad B ¼ 4 ad (b) C ¼ 5 ad B ¼ 4 usig dimiished-1 represetatio: A* 101 C* 100 B* 011 B* 011 C out C out C out 0 C out Correct result 000 result idicatig zero Note that real zero occurs whe the iputs are complimetary. Hece, this coditio eeds to be detected usig logical AND of the exclusive-or of a i ad b i. The EXOR gates will be already preset i the frot-ed CSA stage. Vergos, Efstathiou ad Nikolos have preseted two mod (2 + 1) adder architectures [18] for dimiished-1 umbers. The first oe leads to CLA implemetatio ad was derived by associatig the re-eterig carry equatio with those producig the carries of the modulo additio similar to that for mod (2 1) described earlier [12]. I this architecture, both oe ad two level CLAs have bee cosidered. The secod architecture uses parallel-prefix adders ad also was derived by re-circulatio of the carries i each level of parallel-prefix structure. This architecture avoids the problem of fa-out ad the additioal level eeded i Zimmerma s techique show i Figure 2.6. Efstathiou, Vergos ad Nikolos [14] exteded the above ideas by usig selectprefix blocks which are faster tha the previous oes for desigig mod (2 1) adders for dimiished-1 operads. Here, the legths of the blocks ca be selected appropriately as well as the umber of the blocks. The derivatio is similar to that for mod (2 1) adders with the differece that the equatios cotai block carry propagate, ad block geerate sigals istead of bit level propagate ad geerate sigals. I these, a additioal level is used to add the carry after the prefix computatio. A structure usig two stages is preseted i Figure 2.7. Note that i this case c i, 0 ¼ ðbg 1 þ BP 1 BG 0 Þ 0 c i, 1 ¼ c out, 0 ¼ BG 0 þ BP 0 BG 0 1 These desigs eed lesser area tha desigs usig parallel-prefix adders while they are slower tha CLA-based desigs. Efstathiou, Vergos ad Nikolos [19] have described fast parallel-prefix modulo (2 + 1) adders for two ( + 1)-bit umbers which use two stages. The first stage computes jx þ Y þ 2 1j 2 þ1 which has ( + 2) bits. If MSB of the result is zero, the is added mod 2 +1 ad the LSBs yield the result. For computig M ¼ X þ Y þ 2 1, a CSA is used followed by a ( + 1)-bit adder. The authors use parallel-prefix with fast carry icremet (PPFCI) architecture ad also a totally

11 2.3 Modulo (2 + 1) Adders 19 BG 1 BG 0 BP 1 C i,1 BP 0 C -0 BLOCK 1 Adder (d+f-1:f) BLOCK 0 Adder (f-1:0) Figure 2.7 Dimiished-1 modulo (2 d+f + 1) adder usig two blocks (adapted from [14] IEEE2004) parallel-prefix architecture. I the former, a additioal stage for re-eterig carry is used, whereas i the latter case, carry recirculatio is doe at every prefix level. The architecture of Hiasat [6] ca be exteded to the case of modulus (2 +1)i which case we have Z ¼ 2 1 ad the formulae used are as follows: R ¼ jx þ Y þ Zj 2 if X þ Y þ Z 2 þ1 ad R ¼ jx þ Y þ Zj 2 þ 1 otherwise: Note that, i this case, the added bit z i is always 1 i all bit positios. Vergos ad Efstathiou [20] proposed a adder that caters for both weighted ad dimiished-1 operads. They poit out that a dimiished-1 adder ca be used to realize a weighted adder by havig a frot-ed iverted EAC CSA stage. Herei, A+B is computed where A ad B are ( + 1)-bit umbers usig a dimiished-1 adder. I this desig, the computatio carried out is ja þ Bj 2 þ1 ¼ ja þ B þ D þ 1j 2 þ1 þ 1 2 ¼ jy þ U þ 1j þ1 2 þ1 ð2:14þ where Y ad U are the sum ad carry vector outputs of a CSA stage computig A +B +D: carry sum Y ¼ y 2 y 3 :::::::y o y 1 U ¼ u 1 u 2 :::::::u 1 u o where D ¼ 2 4 þ 2c þ1 þ s. Note that A, B are the words formed by the -bit LSBs of A ad B, respectively, ad s, c +1 are the sum ad carry of additio of 1-bit words a ad b. It may be see that D is the -bit vector 11111:::1c þ1 s. A example will be illustrative. Cosider ¼ 4 ad the additio of A ¼ 16 ad B ¼ 11. Evidetly a ¼ 1, b ¼ 0, A ¼ 0 ad B ¼ 11 ad D ¼ yieldig ( ) 17 ¼ (( ) 17 +1) 17 ¼ 10. Note that the periodic property of residues mod (2 + 1) is used. The sum of the th bits is complimeted ad added to get D ad a correctio term is added to take ito accout the mod (2 + 1) operatio.

12 20 2 Modulo Additio ad Subtractio The mod (2 + 1) adder for weighted represetatio eeds a dimiished-1 adder ad a iverted ed-aroud-carry stage. The full adders of this CSA stage perform (A + B + D) mod (2 + 1) additio. Some of the FAs have oe iput 1 ad ca thus be simplified. The outputs of this stage Y ad U are fed to a dimiished-1 adder to obtai (Y + U + 1) mod 2. The architecture is preseted i Figure 2.8. It ca be see that every dimiished-1 adder ca be used to perform weighted biary additio usig a iverted EAC CSA stage i the frot-ed. a b a b a -1 b -1 a -2 b -2 a -3 b -3 a -4 b -4 a 3 b 3 a 2 b 2 a 1 b 1 a 0 b 0 FA+ FA+ FA+ FA+ FA+ FA+ FA+ FA+ Dimiished-1 adder (ay architecture) S S -1 S -2 S 2 S 1 S 0 Figure 2.8 Modulo (2 + 1) adder for weighted operads built usig a dimiished-1 adder (adapted from [20] IEEE2008)

13 2.3 Modulo (2 + 1) Adders 21 I aother techique due to Vergos ad Bakalis [21], first A* ad B* are computed such that A* + B* ¼ A+B 1 usig a traslator. The, a dimiished-1 adder ca sum A* ad B* such that ja þ Bj 2 þ1 2 ¼ j A* þ B* j 2 þ c out ð2:15þ where c out is the carry of the -bit adder computig A*+B*. However, Vergos ad Bakalis do ot preset the details of obtaiig A* ad B* usig the traslator. Note that i this method, the iputs are (2 1). Li ad Sheu [22] have suggested the use of two parallel adders to fid A*+B* ad A*+B* + 1 so that the carry of the former adder ca be used to select the correct result usig a multiplexer. Note that Li ad Sheu [22] have also suggested partitioig the -bit circular carry selectio (CCS) modular adder to m umber of r-bit blocks similar to the select-prefix block type of desig cosidered earlier. These eed circular carry selectio additio blocks ad circular carry geerators. Juag et al. [23] have give a corrected versio of this type of mod (2 + 1) adder show i Figure 2.9a ad b. Note that this desig uses a dual sum carry look ahead adder (DS-CLA). These desigs are most efficiet amog all the mod (2 +1) adders regardig area, time ad power. Juag et al. [24] have suggested cosiderig ( + 1) bits for iputs A ad B. The weighted modulo (2 + 1) sum of A ad B ca be expressed as ja þ Bj 2 þ1 2 ¼ j A þ B ð 2 þ 1Þj 2 if (A+B) > 2 ¼ ja þ B ð2 þ 1Þj 2 þ 1 otherwise ð2:16þ Thus, weighted modulo (2 + 1) additio ca be obtaied by subtractig the sum of A ad B by (2 + 1) ad usig a dimiished-1 adder to get the fial modulo sum by makig the iverted EAC as carry-i. Deotig Y 0 ad U 0 as the carry ad sum vectors of the summatio A + B (2 + 1), where A ad B are ( + 1)-bit words, we have ja þ B ð2 þ 1Þj 2 ¼ X 2 2 i 2y 0 i þ u0 i þ 2 1 2a þ 2b þ a 1 þ b 1 þ 1 2 where i¼0 y 0 i ¼ a i _ b i, u 0 i ¼ a i b i : As a illustratio, cosider A ¼ 16, B ¼ 15 ad ¼ 4. We have ad for A ¼ 6, B ¼ 7, ja þ B ð2 þ 1Þj 2 ¼ j16 þ 15 17j 16 ¼ 14 ð2:17þ

14 22 2 Modulo Additio ad Subtractio a B * A * C -1 * * { S-1,0...S0,0} DS CLA Adder MUX * * { S-1,1...S0,1} { S-1...S0} * * b * * * * * * * * * * b 3 a 3 b 2 a 2 b 1 a 1 b 0 a 0 p 0 p 1 p* 2 c 3 Modified part MUX MUX MUX MUX p* 3 p* 2 p* 1 s* 3 s* 2 s* 1 s* 0 Figure 2.9 (a) Block diagram of CCS dimiished-1 modulo (2 + 1) adder ad (b) Logic circuit of CCS dimiished-1 modulo ( ) adder ((a) adapted from [22] IEEE2008, (b) adapted from [23] IEEE2009)

15 2.3 Modulo (2 + 1) Adders 23 ja þ B ð2 þ 1Þj 2 ¼ j6 þ 7 17j 16 þ 1 ¼ 13: The multiplier of 2 1 i (2.17) ca be at most 5 sice 0 A, B 2. Sice oly bits ad 1 are available, the authors cosider the ( + 1)-th bit to merge with C out : ja þ Bj 2 þ1 2 ¼ j A þ B ð 2 þ 1Þj 2 ¼ jy 0 þ U 0 j 2 þ c out _ FIX ð2:18þ where y 0 1 ¼ a _ b _ a 1 _ b 1, u 0 1 ¼ a 1 b 1 ad FIX ¼ a b _ a 1 b _a b 1. Note that y 0 1 ad u 0 1 are the values of the carry bit ad sum bit produced by the additio 2a þ 2b þ a 1 þ b 1 þ 1. The block diagram is preseted i Figure 2.10a together with the traslator i b. Note that FAF block geerates y 0 1, u 0 1 ad FA blocks geerate y 0 i, u 0 i for i ¼ 0,1,..., 2 a a b a -1 b -1 a -2 b -2 a 0 b 0 correctio Traslator-(2 +1)=Yʹ+Uʹ FIX Dimiished-1 adder S S -1 S -2 S 0 b a b a -1 b -1 a -2 b -2 a 0 b 0 FAF FA+ FA+ yʹ-1 uʹ-1 yʹ-2 uʹ-2 yʹ0 uʹ0 Figure 2.10 (a) Architecture of weighted modulo (2 + 1) adder with the correctio scheme ad (b) traslator A + B (2 + 1) (adapted from [24] IEEE2010)

16 24 2 Modulo Additio ad Subtractio where y 0 i ¼ a i _ b i ad u 0 i ¼ a i b i. Note also that FIX is wired OR with the carry c out to yield the iverted EAC as the carry i. The FIX bit is eeded sice value greater tha 3 caot be accommodated i y 1 ad u 1. The authors have used Sklasky [25] ad Bret Kug [3] parallel-prefix adders for the dimiished-1 adder. Refereces 1. M.A. Bayoumi, G.A. Jullie, W.C. Miller, A VLSI implemetatio of residue adders. IEEE Tras. Circuits Syst. 34, (1987) 2. M. Dugdale, VLSI implemetatio of residue adders based o biary adders. IEEE Tras. Circuits Syst. 39, (1992) 3. R.P. Bret, H.T. Kug, A regular layout for parallel adders. IEEE Tras. Comput. 31, (1982) 4. G. Alia, E. Martielli, Desigig multi-operad modular adders. Electro. Lett. 32, (1996) 5. K.M. Elleithy, M.A. Bayoumi, A θ(1) algorithm for modulo additio. IEEE Tras. Circuits Syst. 37, (1990) 6. A.A. Hiasat, High-speed ad reduced area modular adder structures for RNS. IEEE Tras. Comput. 51, (2002) 7. C. Efstathiou, D. Nikolos, J. Kalamatiaos, Area-time efficiet modulo 2 1 adder desig. IEEE Tras. Circuits Syst. 41, (1994) 8. R.E. Lader, M.J. Fischer, Parallel-prefix computatio. JACM 27, (1980) 9. P.M. Kogge, H.S. Stoe, A parallel algorithm for efficiet solutio of a geeral class of recurrece equatios. IEEE Tras. Comput. 22, (1973) 10. S. Kowles, A family of adders, i Proceedigs of the 15th IEEE Symposium o Computer Arithmetic, Vail, 11 Jue Jue pp R. Zimmerma, Efficiet VLSI implemetatio of Modulo (2 1) additio ad multiplicatio, Proceedigs of the IEEE Symposium o Computer Arithmetic, Adelaide, 14 April April pp L. Kalampoukas, D. Nikolos, C. Efstathiou, H.T. Vergos, J. Kalamatiaos, High speed parallel prefix modulo (2 1) adders. IEEE Tras. Comput. 49, (2000) 13. A. Tyagi, A reduced area scheme for carry-select adders. IEEE Tras. Comput. 42, (1993) 14. C. Efstathiou, H.T. Vergos, D. Nikolos, Modulo 2 1 adder desig usig select-prefix blocks. IEEE Tras. Comput. 52, (2003) 15. R.A. Patel, S. Boussakta, Fast parallel-prefix architectures for modulo 2 1 additio with a sigle represetatio of zero. IEEE Tras. Comput. 56, (2007) 16. L.M. Liebowitz, A simplified biary arithmetic for the fermat umber trasform. IEEE Tras. ASSP 24, (1976) 17. Z. Wag, G.A. Jullie, W.C. Miller, A efficiet tree architecture for modulo (2 + 1) multiplicatio. J. VLSI Sig. Proc. Syst. 14(3), (1996) 18. H.T. Vergos, C. Efstathiou, D. Nikolos, Dimiished-1 modulo adder desig. IEEE Tras. Comput. 51, (2002) 19. S. Efstathiou, H.T. Vergos, D. Nikolos, Fast parallel prefix modulo (2 + 1) adders. IEEE Tras. Comput. 53, (2004) 20. H.T. Vergos, C. Efstathiou, A uifyig approach for weighted ad dimiished-1 modulo (2 + 1) additio. IEEE Tras. Circuits Syst. II Exp. Briefs 55, (2008)

17 Refereces H.T. Vergos, D. Bakalis, O the use of dimiished-1 adders for weighted modulo (2 +1) arithmetic compoets, Proceedigs of the 11th Euro Micro Coferece o Digital System Desig Architectures, Methods Tools, Parma, 3 5 Sept pp S.H. Li, M.H. Sheu, VLSI desig of dimiished-oe modulo (2 + 1) adders usig circular carry selectio. IEEE Tras. Circuits Syst. 55, (2008) 23. T.B. Juag, M.Y. Tsai, C.C. Chi, Correctios to VLSI desig of dimiished-oe modulo (2 + 1) adders usig circular carry selectio. IEEE Tras. Circuits Syst. 56, (2009) 24. T.-B. Juag, C.-C. Chiu, M.-Y. Tsai, Improved area-efficiet weighted modulo adder desig with simple correctio schemes. IEEE Tras. Circuits Syst. II Exp. Briefs 57, (2010) 25. J. Sklasky, Coditioal sum additio logic. IEEE Tras. Comput. EC-9, (1960)

18