6.111 Lecture 6 Today: 1.Blocking vs. non-blocking assignments 2.Single clock synchronous circuits 3.Finite State Machines

Transcription

1 6. Lecture 6 Today:.Blockig vs. o-blockig assigmets 2.Sigle clock sychroous circuits 3.Fiite State Machies 6. Fall 25 Lecture 6, Slide

2 I. Blockig vs. Noblockig Assigmets Coceptual eed for two kids of assigmet (i always blocks): a b a b c x y Blockig: Evaluatio ad assigmet are immediate No-Blockig: Assigmet is postpoed util all r.h.s. evaluatios are doe Whe to use: ( oly i always blocks! ) a = b b = a a <= b b <= a Sequetial Circuits x = a & b y = x c x <= a & b y <= x c Combiatorial Circuits 6. Fall 25 Lecture 6, Slide 2

3 Assigmet Styles for Sequetial Flip-Flop Based igital elay Lie clk i q q2 out Will oblockig ad blockig assigmets both produce the desired result? module oblockig(i, clk, out); iput i, clk; output out; reg q, q2, out; (posedge clk) begi q <= i; q2 <= q; out <= q2; ed edmodule module blockig(i, clk, out); iput i, clk; output out; reg q, q2, out; (posedge clk) begi q = i; q2 = q; out = q2; ed edmodule 6. Fall 25 Lecture 6, Slide 3

4 Use Noblockig for Sequetial (posedge clk) begi q <= i; q2 <= q; out <= q2; ed At each risig clock edge, q, q2, ad out simultaeously receive the old values of i, q, ad q2. (posedge clk) begi q = i; q2 = q; out = q2; ed At each risig clock edge, q = i. After that, q2 = q = i; After that, out = q2 = q = i; Fially out = i. i q q2 out i q q2 out clk Blockig assigmets do ot reflect the itrisic behavior of multi-stage sequetial logic Guidelie: use oblockig assigmets for sequetial always blocks clk 6. Fall 25 Lecture 6, Slide 4

5 Use Blockig for Combiatioal Blockig Behavior a b c x y (Give) Iitial Coditio a chages; always block triggered x = a & b; y = x c; (a or b or c) begi x = a & b; y = x c; ed a b c x y Noblockig Behavior a b c x y eferred (Give) Iitial Coditio a chages; always block triggered x<= x <= a & b; y <= x c; Assigmet completio x<=, y<= (a or b or c) begi x <= a & b; y <= x c; ed Noblockig assigmets do ot reflect the itrisic behavior of multi-stage combiatioal logic While oblockig assigmets ca be hacked to simulate correctly (expad the sesitivity list), it s ot elegat Guidelie: use blockig assigmets for combiatioal always blocks 6. Fall 25 Lecture 6, Slide 5

6 butto light Implemetatio for o/off butto module ooff(butto,light); iput butto; output light; reg light; (posedge butto) begi light <= ~light; ed edmodule BUTTON LIGHT 6. Fall 25 Lecture 6, Slide 6

7 II. Sigle-clock Sychroous Circuits We ll use Flip Flops ad Registers groups of FFs sharig a clock iput i a highly costraied way to build digital systems. Sigle-clock Sychroous isciplie: No combiatioal cycles Sigle clock sigal shared amog all clocked devices Oly care about value of combiatioal circuits just before risig edge of clock Period greater tha every combiatioal delay Chage saved state after oise-iducig logic trasitios have stopped! 6. Fall 25 Lecture 6, Slide 7

8 Clocked circuit for o/off butto module ooff(clk,butto,light); iput clk,butto; output light; reg light; (posedge clk) begi if (butto) light <= ~light; ed edmodule oes this work with a Mhz? BUTTON LE LIGHT SINGLE GLOBAL CLOCK LOA-ENABLE REGISTER 6. Fall 25 Lecture 6, Slide 8

9 Asychroous Iputs i Sequetial Systems What about exteral sigals? Clock Sequetial System Ca t guaratee setup ad hold times will be met! Whe a asychroous sigal causes a setup/hold violatio... Clock I II III? Trasitio is missed o first clock cycle, but caught o ext clock cycle. Trasitio is caught o first clock cycle. Output is metastable for a idetermiate amout of time. : Which cases are problematic? 6. Fall 25 Lecture 6, Slide 9

10 Asychroous Iputs i Sequetial Systems All of them ca be, if more tha oe happes simultaeously withi the same circuit. Idea: esure that exteral sigals directly feed exactly oe flip-flop Sequetial System Asyc Iput Clocked Sychroous System Clock Clock Clock This prevets the possibility of I ad II occurrig i differet places i the circuit, but what about metastability? 6. Fall 25 Lecture 6, Slide

11 Hadlig Metastability Prevetig metastability turs out to be a impossible problem High gai of digital devices makes it likely that metastable coditios will resolve themselves quickly Solutio to metastability: allow time for sigals to stabilize Likely to be metastable right after samplig Very ulikely to be metastable for > clock cycle Extremely ulikely to be metastable for >2 clock cycle Complicated Sequetial System Clock How may registers are ecessary? epeds o may desig parameters(clock speed, device speeds, ) I 6., a pair of sychroizatio registers is sufficiet 6. Fall 25 Lecture 6, Slide

12 III. Fiite State Machies Fiite State Machies (FSMs) are a useful abstractio for sequetial circuits with cetralized states of operatio At each clock edge, combiatioal logic computes outputs ad ext state as a fuctio of iputs ad preset state iputs + preset state Combiatioal outputs + ext state Flip- Flops 6. Fall 25 Lecture 6, Slide 2

13 State trasitio diagram Example : Light Switch BUTTON= BUTTON= LIGHT = LIGHT = BUTTON= BUTTON= diagram Combiatorial logic BUTTON LIGHT Register 6. Fall 25 Lecture 6, Slide 3

14 Two Types of FSMs Moore ad Mealy FSMs : differet output geeratio Moore FSM: iputs x...x Comb. ext state S + Flip- Flops Comb. outputs y k = f k (S) preset state S Mealy FSM: iputs x...x Comb. direct combiatioal path! S + Flip- Flops Comb. outputs y k = f k (S, x...x ) S 6. Fall 25 Lecture 6, Slide 7

15 esig Example: Level-to-Pulse A level-to-pulse coverter produces a sigle-cycle pulse each time its iput goes high. It s a sychroous risig-edge detector. Sample uses: Buttos ad switches pressed by humas for arbitrary periods of time Sigle-cycle eable sigals for couters Wheever iput L goes from low to high... L Level to Pulse Coverter P...output P produces a sigle pulse, oe clock period wide. 6. Fall 25 Lecture 6, Slide 8

16 Step : State Trasitio iagram Block diagram of desired system: Sychroizer Edge etector usychroized user iput L Level to Pulse FSM P State trasitio diagram is a useful FSM represetatio ad desig aid: if L= at the clock edge, the jump to state. L= L= Biary values of states L= if L= at the clock edge, the stay i state. Low iput, Waitig for rise P = L= Edge etected! P = L= High iput, Waitig for fall P = L= This is the output that results from this state. (Moore or Mealy?) 6. Fall 25 Lecture 6, Slide 9

17 Step 2: erivatio Trasitio diagram is readily coverted to a state trasitio table (just a truth table) L= Low iput, Waitig for rise P = L= L= L= Edge etected! P = L= High iput, Waitig for fall P = L= Curre t State I Next State Combiatioal logic may be derived usig Karaugh maps S S L S + S + Out P S S L S S L for S + : X X for S + : X X L Comb. S + = LS S + = L S + S Flip- Flops Comb. P = S S P S S for P: X 6. Fall 25 Lecture 6, Slide 2

18 Moore Level-to-Pulse Coverter iputs x...x Comb. ext state S + Flip- Flops Comb. outputs y k = f k (S) S + = LS S + = L preset state S P = S S Moore FSM circuit implemetatio of level-to-pulse coverter: L S + S P S + S 6. Fall 25 Lecture 6, Slide 23

19 esig of a Mealy Level-to-Pulse Comb. direct combiatioal path! S + S Flip- Flops Comb. Sice outputs are determied by state ad iputs, Mealy FSMs may eed fewer states tha Moore FSM implemetatios. Whe L= ad S=, this output is asserted immediately ad util the state trasitio occurs (or L chages). L= P= Iput is low L= P= L= P= Iput is high L= P= L P Clock State Output trasitios immediately. State trasitios at the clock edge After the trasitio to S= ad as log as L remais at, this output is asserted. 6. Fall 25 Lecture 6, Slide 24

20 Mealy Level-to-Pulse Coverter L= P= Iput is low L= P= L= P= Iput is high L= P= Pres. State S I L Next State S + Out P Mealy FSM circuit implemetatio of level-to-pulse coverter: P L S + S S FSM s state simply remembers the previous value of L Circuit beefits from the Mealy FSM s implicit siglecycle assertio of outputs durig state trasitios 6. Fall 25 Lecture 6, Slide 26

21 Moore/Mealy Trade-Offs How are they differet? Moore: outputs = f( state ) oly Mealy outputs = f( state ad iput ) Mealy outputs geerally occur oe cycle earlier tha a Moore: Moore: delayed assertio of P L P Clock State[] Mealy: immediate assertio of P L P Clock State Compared to a Moore FSM, a Mealy FSM might... Be more difficult to coceptualize ad desig Have fewer states 6. Fall 25 Lecture 6, Slide 27

22 FSM Timig Requiremets Timig requiremets for FSM are idetical to ay geeric sequetial system with feedback Miimum Clock Period Miimum elay iputs + preset state Combiatioal T logic outputs + ext state iputs + preset state Combiatioal T cd,logic outputs + ext state T cq T cd,reg Flip- Flops T su Flip- Flops T hold T T > T cq + T logic + T su T cd,reg + T cd,logic > T hold 6. Fall 25 Lecture 6, Slide 28

23 Summary Assigmets i always blocks: blockig ( = ) for combiatioal logic o-blockig ( <= ) for sequetial logic Sigle-clock Sychroous disciplie: Reliable digital circuits / systems Global clock to edge-triggered registers Fiite state machies: Programmable systems Moore & Mealy Combiatioal Flip- Flops 6. Fall 25 Lecture 6, Slide 29