CMOS. Dynamic Logic Circuits. Chapter 9. Digital Integrated Circuits Analysis and Design

Transcription

1 MOS Digital Itegrated ircuits Aalysis ad Desig hapter 9 Dyamic Logic ircuits 1

2 Itroductio Static logic circuit Output correspodig to the iput voltage after a certai time delay Preservig its output level as log as the power supply is provided Large area time delay Dyamic logic circuit he operatio of all dyamic logic gates depeds o temporary (trasiet) storage of charge i parasitic ode capacitaces Need periodic clock sigals charge refreshig Smaller silico area osume less power

3 Eample 9.1 K1 MP o chargig or dischargig QD K0 MP off isolated from D Q (deped o the charge store i ) d iverter remove rasistor couts Q-D Assumig OL0 IL.1 IH.9 OH K1 MP o ioh higher tha IH so Q K0 M off 4. if charge leakage <.9 ca t be iterpreted as a logic 1 3

4 Basic priciples of pass trasistor circuits he fudametal buildig block of MOS dyamic logic circuits MP A MOS pass trasistor drivig the gate of aother MOS trasistor Drivig by the periodic clock sigal Acts as access switch If K1 Logic 1 trasfer Logic 0 trasfer If K0 ease to coduct ad the charge store I the parasitic capacitace 4

5 5 Logic 1 trasfer ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) F F t t t k t k t k t k d k dt k φ φ γ 1 ) ( dt d to charge up the MP o i saturatio regio starts 1 0 K : 0 0) (t Itially ma 0 ma OH i + + he ode has a upper limit of ma ( - )

6 6 Logic 1 trasfer ( ) ( ).... ma 0 ma1 0 1 F F F F φ φ γ φ φ γ + +

7 7 Logic 0 trasfer ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) [ ] ( ) fall t k k t t k t k k t k t k t d k dt d k dt k dt d 90% 10% 10% 90% 0.74 l(1.) l(19) l l ) 0.9( ) 0.9)( ( l l l τ he pass trasistor operates i the liear regio throughout this cycle sice DS < GS -

8 harge storage ad charge leakage I leakage I subthreshold(mp) +I reverse(mp) 8

9 Equivalet circuit used for aalyzig the charge leakage process Q Q ( i dq dq j( ) dqi Ileakage + dt dt dt dq j( ) A j0 where j ( ) d 1+ φ k N D N φ l 0 q i + t mi hold j gb ΔQ I ) + Q + gb i poly criticalmi leakagema + poly where Q + A metal j0 metal i + where ΔQ i 0 qε SiN A ( N + N ) A dbmi criticalmi A N D D mi qε SiN 0 ( φ + ) 0 ma A qε SiN φ i : these costat capacitace compoets : due to reverse biased drai-substrate juctio mi : the miimum combied soft-ode capacitace db.mim : the miimum juctio capacitace obtaied uder the bias coditio ma t hold : worst-case holdig time the shortest time required for the soft-ode voltage to drop from the iitial logic high value to the logic threshold voltage due to leakage φ 0 A 9

10 Eample 10

11 Eample (cot.) 11

12 oltage bootstrappig o overcome threshold voltage drops i digital circuits Figure 9.11 osiderig M i saturatio out(ma) - (out) o obtai a full logic-high level the voltage must be icreased Figure 9.1 A third trasistor has bee added to the circuit s : dyamic couple to the groud boot : dyamic couple to his circuit produce a high durig switchig + ( out ) 1

13 oltage bootstrappig i s ( + ) s if 3 (mi) ( + ) s i boot s boot boot boot boot d boot 3 d dt ( ) s ( + ) out 3 ( + ) OL ( + ) + s OL d dt boot OU OU ( OU boot boot boot d dt OU out OL is much larger tha + + ( ( )) 3 3 d( out ) dt d dt ) d s ( ma ) 3 3 s ( boot + boot - ( + ) *s: the sum of the parasitic source-to-substrate cap. ofm3 ad the gate-to substrate cap of M *o obtai a sufficietly large bootstrap cap. boot i compariso to s a etra dummy trasistor is added *he dummy trasistor acts as a MOS capacitor betwee ad out s 3 d dt boot - out ) + OL boot s ( boot boot OL ( ) OL ) 13

14 Eample

15 Sychroous dyamic circuit techiques Previous sectio Basic cocepts associated with temporary storage of logic levels i capacitive circuit odes his sectio Pay attetio to digital circuit desig Differet eamples of sychroous dyamic circuit Depletio-load MOS Ehacemet-load MOS MOS buildig block 15

16 Dyamic pass trasistor circuits ascaded combiatioal logic stage Itercoected through MOS trasistor All iput of each combiatioal logic block are drive by a sigle clock sigal wo phase clockig 16

17 Depletio-load MOS dyamic shift register circuit Φ1 active i is trasferred to i1 out1 is determied Φ active out1 is trasferred to i out is determied i1 retai its previous level via charge storage Φ1 active agai he origial data bit writte ito the register (3rd)!st stage accept ew data 17

18 Depletio-load MOS dyamic shift register circuit Maimum clock frequecy Beig determied by the sigal propagatio delay through oe iverter stage Oe half period of the clock sigal must be log eough to allow i to charge up or dow ad the logic level to propagate to the output by chargig out Logic-high iput level of each iverter stage is oe threshold voltage lower tha the power supply level 18

19 A two-stage sychroous comple logic circuit he same operatio priciple eteded to sychroous comple logic I order to guaratee correct logic levels are propagated durig each active clock cycle he half period legth of the clock sigal must be loger tha the largest sigal-stage sigal propagatio delay foud i the cirucit 19

20 Ehacemet-load dyamic shift register (ratioed logic)(1) Oe importat differece Applyig the clock sigal to the gate of the load trasistor Power dissipatio ad the silico area ca be reduced sigificatly he iput pass trasistor ad load trasistor are drive by opposite clock phase 0

21 Ehacemet-load dyamic shift register (ratioed logic)() Φ1 active i i1 MOS load off Φ active MOS load o the output of 1st iverter attais its valid logic (i1 preserved) Pass trasistor of d stage o out1 i Φ1 active out is determied ad trasferred ito i3 Also a ew iput level ca be accepted ito i1 OL of each stage is strictly determied by the driver to load ratio (ratioeddyamic logic) 1

22 Geeral circuit structure of ratioed sychroous dyamic logic Eteded to arbitrary comple logic

23 Ehacemet-load dyamic shift register (ratioless logic)(1) I each stage the iput pass trasistor ad the load trasistor are drive by the same clock phase Φ1 active i trasfer to i 1st iverter is active out1 attais its valid logic level Φ active d pass trasistor o the logic level is trasferred oto the et stage 3

24 Ehacemet-load dyamic shift register (ratioless logic)() osiderig two cases ase 1 If out1 high at the ed of the active Φ1 phase By mea of i1 low iput MOS driver off out1- Φ active he voltage level is trasfer to i via charge sharig over the pass trasistor out/i to correctly trasfer a logic-high level 4

25 Ehacemet-load dyamic shift register (ratioless logic)(3) osiderig two cases ase If out1 is logic-low at the ed of the active Φ1 phase i1 high MOS driver o out10 As Φ active rasfer by pass trasistor Ratioless dyamic logic OL 0 idepedet of driver-to-load ratio 5

26 Geeral circuit structure of ratioless sychroous dyamic logic 6

27 Dyamic MOS trasmissio gate logic otally require four clock sigals 7

28 MOS trasmissio gate dyamic shift register Low o-resistace of trasmissio gate (ref.p310) Smaller trasfer time (R ) No threshold voltage drop 8

29 Sigle-phase MOS trasmissio gate dyamic shift register Ideally K1 Odd o eve off isolated I practical do ot truly ooverlappig LK have fiite t r ad t f So prefer Φ1 Φ 9

30 Dyamic MOS logic gate implemetig a comple Boolea fuctio(1) ( A A A B ) F B Sigificatly reduce the umber of trasistors used to implemet ay logic fuctio Operatio First prechargig the output ode capacitace Evaluatig the output level accordig to the applied iputs Both of theses of operatios are scheduled by a sigle clock sigal Which drives oe MOS ad oe pmos trasistor i each dyamic stage 30

31 Dyamic MOS logic gate implemetig a comple Boolea fuctio() Φ0 (precharge phase) Mp o Me off the parasitic capacitace of the circuit is charged up to out he iput voltages are also applied durig this phase o ifluece o the output Φ1 (evaluate phase) Mp off Me o the output voltage deped o the iput voltage levels OL or he practical multi-stage applicatios however the dyamic MOS gate presets a sigificat problem 31

32 Illustratio of the cascadig problem i dyamic MOS logic(1) Assume Durig the precharge phase Both output voltages out1 ad out are pulled up Durig evaluatio phase he iput variables of 1st stage assume to be such that Output out1 drop to logic 0 he eteral iput of d stage assume to be logic 1 As evaluatio Begiig Both out1 a d out are logic-high he out1 drops to its correct logic after a certai time delay out Startig with the high value of out1 at the begiig of the evaluatio phase the output voltage out at the ed of the evaluatio phase will be erroeously low 3

33 Illustratio of the cascadig problem i dyamic MOS logic(1) his eample illustrates that Dyamic MOS logic gates drive by the same clock sigal caot be cascade directly his limitatio udermie some advatages such as Low power dissipatio Large oise margis Low trasistor cout 33

34 High-performace dyamic MOS circuits Base o the basic dyamic MOS logic gate structure Desig to take full advatage of the obvious beefits of dyamic operatio o all urestricted cascadig of multiple stages he ultimate goal is to achieve usig the least complicated clockig scheme possible Reliable High-speed ompact circuit 34

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