Summary of pn-junction (Lec )

Transcription

1 Lecture #12 OUTLNE Diode aalysis ad applicatios cotiued The MOFET The MOFET as a cotrolled resistor Pich-off ad curret saturatio Chael-legth modulatio Velocity saturatio i a short-chael MOFET Readig Howe ad odii Chap (page ) Hambley Chapter 10 EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 1 ummary of p-juctio (Lec ) Two major currets i a p juctio Diffusio curret: carriers flow from where there are may to where there are few Electros diffuse from -side to p-side ad holes diffuse from p-side to -side both result i positive curret from p to side Drift curret: carriers flow due to electric field Electric field exists i the depletio regio oly (this is the depletio approximatio) Electric field poits from side to p side, sweepig electros from p- side (miority) to -side ad holes from -side (miority also) to p- side resultig positive curret from to p side D V D p EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 2 1

2 ummary of p-juctio (Lec ) Uder zero bias (0V), the two currets are equal et curret D =0 Uder forward bias, the potetial barrier is reduced drift curret is reduced ad diffusio curret icreases (positive et curret) Curret D icreases expoetially with icreasig forward bias The carriers become miority carriers oce they cross the juctio; as they diffuse i the quasi-eutral regios, they recombie with majority carriers (supplied by the metal cotacts) Uder reverse bias, the potetial barrier is icreased drift curret domiates (egative et curret) But sice the carriers that create drift currets are miority carriers, drift curret is carrier limited ad remais to be very small ad saturates with large reverse bias V D (A) V D (V) EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 3 How to Aalyze Circuits with Diodes A diode has oly two states: forward biased: D > 0, V D = 0 V (or 0.7 V) reverse biased: D =0, V D < 0 V (or 0.7 V) Procedure: 1. Guess the state(s) of the diode(s) 2. Check to see if KCL ad KVL are obeyed. 3. f KCL ad KVL are ot obeyed, refie your guess 4. Repeat steps 1-3 util KCL ad KVL are obeyed. Example: v s (t) v R (t) f v s (t) > 0 V, diode is forward biased (else KVL is disobeyed try it) f v s (t) < 0 V, diode is reverse biased (else KVL is disobeyed try it) EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 4 2

3 Load Lie Aalysis Method Very powerful techique complicated liear circuits ca be reduce to Thevei circuit (Lec. 4) Graph the -V relatioships for the o-liear elemet (e.g. diode) ad for the rest of the circuit (Thevei Voltage ad Resistor) The operatig poit of the circuit is foud from the itersectio of these two curves. R Th V Th /R Th operatig poit V Th V V The -V characteristic of all of the circuit except the o-liear elemet is called the load lie EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 5 V Th Light Emittig Diode (LED) LEDs are made of compoud semicoductor materials Carriers diffuse across a forward-biased juctio ad recombie i the quasi-eutral regios optical emissio EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 6 3

4 olar cell: Example of simple PN juctio What is a solar cell? Device that coverts sulight ito electricity How does it work? simple cofiguratio, it is a diode made of PN juctio cidet light is absorbed by material Creates electro-hole pairs that trasport through the material through Diffusio (cocetratio gradiet) Drift (due to electric field) PN Juctio Diode EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 7 Optoelectroic Diodes (cot d) Light icidet o a p juctio geerates electro-hole pairs The miority carriers that are geerated i the depletio regio, ad the miority carriers that are geerated i the quasi-eutral regios ad the diffuse ito the depletio regio, are swept across the juctio by the electric field This results i a additioal compoet of curret flowig i the diode: qvd kt D = ( e 1) optical where optical is proportioal to the itesity of the light EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 8 4

5 Photovoltaic (olar) Cell D qvd kt = ( e 1) optical D (A) i the dark V D (V) with icidet light operatig poit EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 9 Photodiode A itrisic regio is placed betwee the p-type ad -type regios W j W i-regio, so that most of the electro-hole pairs are geerated i the depletio regio faster respose time (~10 GHz operatio) D (A) i the dark operatig poit V D (V) with icidet light EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 10 5

6 Photodetector Circuit Usig Load Lie V Th R Th V operatig poits uder differet light coditios. As light itesity icreases. Why? As light shies o the photodiode, carriers are geerated by absorptio. These excess carriers are swept by the electric field at the juctio creatig drift curret, which is same directio as the reverse bias curret ad hece egative curret. The curret is proportioal to light itesity ad hece ca provide a direct measuremet of light itesity photodetector. V Th V Th /R Th load lie V - What happes whe R th is too large? - Why use Vth? EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 11 Diodes i Circuits Use piece-wise liear model EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 12 6

7 Power Coversio Circuits Covertig AC to DC Potetial applicatios: Chargig a battery V =V m si (ωt) R V o EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 13 Equivalet circuit V>0.6V, diode = short circuit V o =V -0.6 V<0.6V, diode = ope circuit Vo=0 EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 14 7

8 Half-wave Rectifier Circuits Addig a capacitor: what does it do? V m si (ωt) C R V 0 - EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 15 Half-wave Rectifier Curret chargig up capacitor EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 16 8

9 Why are p Juctios mportat for Cs? The basic buildig block i digital Cs is the MO trasistor, whose structure cotais reverse-biased diodes. p juctios are importat for electrical isolatio of trasistors located ext to each other at the surface of a i wafer. The juctio capacitace of these diodes ca limit the performace (operatig speed) of digital circuits EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 17 Device solatio usig p Juctios regios of -type i p-type i No curret flows if voltages are applied betwee -type regios, because two p juctios are back-to-back -regio -regio p-regio => -type regios isolated i p-type substrate ad vice versa EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 18 9

10 Trasistor A Trasistor B p-type i We ca build large circuits cosistig of may trasistors without worryig about curret flow betwee devices. The p- juctios isolate the trasistors because there is always at least oe reverse-biased p- juctio i every potetial curret path. EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 19 Moder Field Effect Trasistor (FET) A electric field is applied ormal to the surface of the semicoductor (by applyig a voltage to a overlyig gate electrode), to modulate the coductace of the semicoductor Modulate drift curret flowig betwee 2 cotacts ( source ad drai ) by varyig the voltage o the gate electrode Metal-oxide-semicoductor (MO) FET: EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 20 10

11 MOFET NMO: N-chael Metal Oxide emicoductor W GATE L = chael legth W = chael width L Metal (heavily doped poly-i) oxide isulator p-type silico DRAN OURCE A GATE electrode is placed above (electrically isulated from) the silico surface, ad is used to cotrol the resistace betwee the OURCE ad DRAN regios EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 21 N-chael MOFET G D gate oxide isulator p Without a gate voltage applied, o curret ca flow betwee the source ad drai regios. Above a certai gate-to-source voltage (threshold voltage V T ), a coductig layer of mobile electros is formed at the i surface beeath the oxide. These electros ca carry curret betwee the source ad drai. EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 22 11

12 N-chael vs. P-chael MOFETs NMO poly-i PMO p poly-i p p p-type i -type i For curret to flow, V G > V T Ehacemet mode: V T > 0 Depletio mode: V T < 0 Trasistor is ON whe V G =0V For curret to flow, V G < V T Ehacemet mode: V T < 0 Depletio mode: V T > 0 Trasistor is ON whe V G =0V ( deotes very heavily doped -type material; p deotes very heavily doped p-type material) EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 23 MOFET Circuit ymbols NMO G G poly-i p-type i PMO p poly-i G G p p -type i EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 24 12

13 MOFET Termials The voltage applied to the GATE termial determies whether curret ca flow betwee the OURCE & DRAN termials. For a -chael MOFET, the OURCE is biased at a lower potetial (ofte 0 V) tha the DRAN (Electros flow from OURCE to DRAN whe V G > V T ) For a p-chael MOFET, the OURCE is biased at a higher potetial (ofte the supply voltage V DD ) tha the DRAN (Holes flow from OURCE to DRAN whe V G < V T ) The BODY termial is usually coected to a fixed potetial. For a -chael MOFET, the BODY is coected to 0 V For a p-chael MOFET, the BODY is coected to V DD EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 25 NMOFET G vs. V G Characteristic Cosider the curret G (flowig ito G) versus V G : V G G G D oxide semicoductor V D G always zero! The gate is isulated from the semicoductor, so there is o sigificat (steady) gate curret. V G EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 26 13

14 The MOFET as a Cotrolled Resistor The MOFET behaves as a resistor whe V D is low: Drai curret D icreases liearly with V D Resistace R D betwee OURCE & DRAN depeds o V G R D is lowered as V G icreases above V T oxide thickess t ox NMOFET Example: D V G = 2 V V G = 1 V > V T V D D = 0 if V G < V T versio charge desity Q i (x) = -C ox [V G -V T -V(x)] where C ox ε ox / t ox EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 27 heet Resistace Revisited Cosider a sample of -type semicoductor: V _ W homogeeously doped sample t L R s ρ = = = = t σt qμ t μ Q where Q is the charge per uit area EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 28 14

15 NMOFET D vs. V D Characteristics Next cosider D (flowig ito D) versus V D, as V G is varied: V G G D oxide semicoductor D V D D V G > V T zero if V G < V T V D Above threshold (V G > V T ): iversio layer of electros appears, so coductio betwee ad D is possible Below threshold (V G < V T ): o charge o coductio EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 29 MOFET as a Cotrolled Resistor (cot d) V D = R R D D D = R ( L / W ) = s L / W μ Q We ca make R D low by i μ C ( V L / W applyig a large gate drive (V G V T ) makig W large ad/or L small = ox G V 2 V D D Cox ( VG VT ) = μ W L T V V 2 D D ) average value of V(x) EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 30 15

16 Charge i a N-Chael MOFET V G < V T : depletio regio (o iversio layer at surface) V G > V T : V D 0 V D > 0 (small) D = WQ = WQ = WQ iv iv μ iv v E V μ L D Average electro velocity v is proportioal to lateral electric field E EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 31 What Happes at Larger V D? V G > V T : V D = V G V T versio-layer is piched-off at the drai ed V D > V G V T As V D icreases above V G V T V DAT, the legth of the pich-off regio ΔL icreases: extra voltage (V D V Dsat ) is dropped across the distace ΔL the voltage dropped across the iversio-layer resistor remais V Dsat the drai curret D saturates Note: Electros are swept ito the drai by the E-field whe they eter the pich-off regio. EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 32 16

17 ummary of D vs. V D As V D icreases, the iversio-layer charge desity at the drai ed of the chael is reduced; therefore, D does ot icrease liearly with V D. Whe V D reaches V G V T, the chael is piched off at the drai ed, ad D saturates (i.e. it does ot icrease with further icreases i V D ). V G G V D > V G - V T D DAT = μ C ox W 2L ( V V ) 2 G T - V G - V T pich-off regio EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 33 D vs. V D Characteristics The MOFET D -V D curve cosists of two regios: 1) Resistive or Triode Regio: 0 < V D < V G V T D = k W L where k 2) aturatio Regio: V D > V G V T k W DAT = VG V 2 L where k = μ C VG V = μ C ( ) ox ox T V 2 T D 2 V process trascoductace parameter D CUTOFF regio: V G < V T EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 34 17

18 Chael-Legth Modulatio f L is small, the effect of ΔL to reduce the iversio-layer resistor legth is sigificat D icreases oticeably with ΔL (i.e. with V D ) D D = D (1 λv D ) λ is the slope D is the itercept V D EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 35 P-Chael MOFET D vs. V D As compared to a -chael MOFET, the sigs of all the voltages ad the currets are reversed: hort-chael PMOFET -V Note that the effects of velocity saturatio are less proouced tha for a NMOFET. Why is this the case? EE40 ummer 2005: Lecture 12 structor: Octavia Florescu 36 18