Semiconductor Electronic Devices

Transcription

1 Semicoductor lectroic evices Course Codes: 3 (UG) 818 (PG) Lecturer: Professor thoy O eill mail: athoy.oeill@cl.ac.uk ddress: 4.31, Merz Court ims: To provide a specialist kowledge of semicoductor devices. To eable studets to have a better uderstadig of state-of- the - art MOSFT ad bipolar trasistors. To eable studets to compare competig semicoductor techologies.

2 Silico lectroic evices Si is the workhorse techology (~99% of market) Cheap, well-developed evice scalig => higher performace devices May challeges ahead

3 Trasistors are the buildig block Itel 45 m CMOS 35 m types: Bipolar (p, pp) % market MOSFT (CMOS) 8% market Used for: alog e.g. amplificatio igital O or OFF

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9 How far ca scalig go?

10 Quotes I thik there is a world market for maybe five computers Thomas Watso, Chairma of IBM, 1943 Computers i the future may weigh o more tha 1.5 tos Popular Mechaics, K ought to be eough memory for aybody Bill Gates, 1981

11 Why itegrate circuits? create jobs? faster? more fuctioality? cheaper?

12 lectric Field Lies esity of lies is proportioal to magitude of ad i directio of ll lies origiate at a + charge ad are cotiuous to a - charge

13 Gauss s Law. ds Q ec raw a Gaussia surface most coveiet to solve the problem:. ds rea 4r Q 4 r Q ec Q Q ec Coulomb s Law r Q

14 Gaussia Surface ll Gaussia surfaces are correct, but ot always helpful Q Q

15 Gaussia Surface

16 lectrostatics - assumed Kowledge Q Q. CV, C. ds ddydz Q ec dq dv d d efiitio of capacitace Charge ad charge desity isplacemet vector lectric field ad potetial gradiet Gauss s Law (itegral form) Gauss s Law (differetial form) Poisso quatio

17 ergy Bads atom has discrete eergy levels

18 ergy Bads atoms have doublet eergy levels

19 ergy Bads 3 atoms have triplet eergy levels, etc.

20 ergy Bads ~ mpty C v ~ Full may atoms i crystal eergy bads

21 ergy Bads: Fermi-irac istributio Probability The Fermi-irac distributio f() is the probability that a electro (or hole) may occupy a available eergy state 1 f ( ) F 1 ep kt If >> F the f() lectro states empty above F If << F the f() 1 lectro states fully occupied below F If = F the f().5 1% 1% 8% 6% 4% % % valece V C F (ev) coductio occupatio probability is 5% for states at Fermi ergy F

22 Carrier esity,, p The electro desity,, is the desity of electro states () ad the probability that each state is occupied f() summed over all eergies i the coductio bad: ( ) F C ( ) f ( ) d d C ep C F kt C1 ep kt The hole desity, p, is the desity of electro states ad the probability that each state is OT occupied summed over all eergies i the valece bad: p V ( )(1 f ( )) d V ep V kt F where C, V are the effective desity of states i the coductio bad, valece bad

23 For itrisic (udoped) semicoductors the Fermi ergy F is desigated i kt q kt kt kt kt f i i F i C F C i i C i C i ep ep ep ep ep kt kt p g V C i F V C F V C i ep ep kt q p kt p kt kt p kt p f i F i i F V i V i i V V i ep ep ep ep ep Itrisic Semicoductor

24 ergy-mometum Relatio Kietic ergy: 1 ( mv) mv m I quatum mechaics, So mometum, m k mv k Plot of versus k is ~ parabolic lectro mass, m* is estimated from bad curvature: m * d dk 1

25 Probability Probability Probability trisic (oped or P type) Semicoductor 1% 8% 6% 4% valece V F coductio C Itrisic: F mid-gap = p 1% 8% 6% 4% % % -.3 1% F F (ev) 8% 6% 4% % % F F (ev) Type: Use door ios + Shallow eergy level, F close to c >> p P Type: Use acceptor ios - Shallow eergy level, % % F (ev) F close to V <<p

26 Itrisic Carrier Cocetratio s temperature icreases, the itrisic carrier cocetratio washes out the etrisic dopig The mil-spec limit for Si techology is 15 C (4 K) i (cm -3 ) Si Ge Gas Temperature (K)

27 . What is the itrisic carrier cocetratio of silico at the mil. spec temperature of 15 C? i i C V ep kt cm 3 g ep (73 15)

28 Metal-Semicoductor Juctio Metal ad semicoductor far apart: metal semicoductor W M W S C F F V Workfuctio W: eergy eeded to take electro from Fermi eergy ( F ) to Vacuum level ( ) lectro ffiity : eergy eeded to take electro from the coductio bad miimum to vacuum level W ( F ) S C

29 Metal-Semicoductor Juctio Brig metal ad semicoductor ito itimate cotact q bi W M q b W S F C F ioized dopig ios depletio regio V Built-i voltage is: bi 1 W M WS q 1 Schottky barrier height is: b W M q I practice Schottky barrier height is measured directly, presece of surface states meas simple theory ca fail

30 etermie depletio layer thickess, d Solve Poisso s quatio: Itegrate, Boudary Coditio = at = d Itegrate, Boudary Coditio = at = d s d d ) ( ) ( ) ( q d d S q d d d s

31 Obtai d by demadig () = - bi The q ( ) d d bi S q S q d d S d d s bi q depletio barrier d (mm) phi =.1 V phi =.5 V phi = 1V opig (cm -3 )

32 . Schottky barrier is formed by a metal cotact o cm -3 doped Gas. Calculate the depletio regio thickess if the built-i potetial is.7 V. epletio thickess is d s q bi mm 1 3.7

33 potetial Schottky Cotact Low/moderate dopig, barrier height coductio over barrier ~ o tuellig similar to diode: rectifyig Schottky diode Trasistor gate =1 16 cm -3 thermioic emissio tuellig depth (um)

34 potetial Ohmic Cotact High dopig, low barrier height Tuellig curret Ohmic coductio small resistace ρ c ~ 1-7.cm Meas of electrical commuicatio with the outside world =1 cm -3 thermioic emissio tuellig depth (um)

35 p juctio electros ad holes recombie together at the juctio, creatig a space charge regio which oly has ioized door () or acceptor (P) ios. lsewhere -ve electro charge balaces +ve doors atoms or +ve hole charge balaces -ve acceptor atoms V bi W, depletio width V bi

36 p- juctio From metal-semicoductor depletio layer aalysis: Treatig depletio regio edge as Gaussia surface: type p-type p S bi q p S p bi q p p ec Q ds. S p S bi q q V

37 p- juctio epletio layer thickesses: similarly: epletio width, bi S p bi S p S p p S p S bi q V q V q q q V 1 bi S q V bi S p q V W bi S bi S q V q V W

38 Summary Brief history semicoductor devices lectrostatics ergy bads Semicoductors ergy bads, carrier desity, dopig, metal-semicoductor juctio, p- juctio