EE C245 - ME C218 Introduction to MEMS Design Fall Today s Lecture

Transcription

1 EE C45 ME C8 Itroductio to MEMS Desig Fall 003 Roger Howe ad Thara Sriiasa Lecture 3 Capacitie Positio Sesig: Electroic ad Mechaical Noise EE C45 ME C8 Fall 003 Lecture 3 Today s Lecture Basic CMOS buffer amplifiers for positio sesig Electroic oise sources: trasistors ad resistors Browia oise Sigaltooise ratio Readig: Gray, P.R., ad Meyer, R. G., Aalysis ad Desig of Aalog Itegrated Circuits, 3 rd Ed., 993. EE C45 ME C8 Fall 003 Lecture 3

2 C () The Capacitie HalfBridge, Reisited ( t) = Vˆ C i 0 X out C () = ε o A/(g o ) C () = ε o A/(g o ) C () ( t) = Vˆ How do we desig a X buffer with C i 0? Z Z V = Vˆ ( ) Vˆ ( ) out Z Z ( ) Z ( ) Z V out = V i = Vˆ g o EE C45 ME C8 Fall 003 Lecture 3 3 Precisio Uity Gai ia Feedback V DD out =A d ( ), A d is large i = i = out out = A d ( i out ) out Ad = A d i i EE C45 ME C8 Fall 003 Lecture 3 4

3 Basic CMOS Differetial Amplifier B V DD I SS / Simplified aalysis: = = ( )/ M M out A b i,d r o,cs out I SS r o g m gs gs a EE C45 ME C8 Fall 003 Lecture 3 Nodes a ad b are icremetal grouds 5 Differetial Gai A d out r o g m gs gs out = (g m gs )r o out = g m r o i.d = = Typical alues g m r o = 00 A d = 00 out = g m r o ( i,d /) out = (g m r o /) i,d A d EE C45 ME C8 Fall 003 Lecture 3 6 3

4 Basic UityGai Buffer V DD I SS / shortcircuit output to iertig iput Z i M M out i I SS Iput resistace R i = Ω Iput capacitace = C i =? EE C45 ME C8 Fall 003 Lecture 3 7 Iput Capacitace C i C i C gd V i V g mv gs r o gs C gs r o r o,cs gatedrai short o trasistor M g m V gs =g m V ds r o,cs Resistor R = (g m ) r o r o,cs Equialet to a resistor = (g m ) Therefore, V gs 0 V phasor curret through C gs 0 A C gs does t eist (it s bee bootstrapped ). I practice, C gs is reduced 00 fold. R Iput capacitace is due to gatedrai capacitace of M : EE C45 ME C8 Fall 003 Lecture 3 C i C gd 8 4

5 Improed UityGai Buffer V DD Weijie Yu, Ph.D. EECS, 99 M 3 M 4 I SS / M 3, M 4 cause V d to track V i C gd is bootstrapped, too! Z i M M out i I SS Result: C i approaches zero. EE C45 ME C8 Fall 003 Lecture 3 9 V DD Settig the DC Bias ( t) = Vˆ C () C () ( t) = Vˆ A M 3 M 4 I SS I SS / M M Node A has o path to groud; so it s called a floatig ode out Solutios:. W. Yu ad G. K. Fedder: zerobiased diode to leak A to a kow DC oltage (e.g., V DD /). W. Clark, M. Palaiapa: MOSFET biased i subthreshold to set A to DC potetial of M s drai. 3. M. Lemki: MOSFET switch EE C45 ME C8 Fall 003 Lecture 3 0 5

6 Electroic Noise Sources. Thermal oise i resistors geerated by radom motio of electros or holes white spectral desity (up to 0 THz) = 4k TR f B spectral desity / f = 4k TR Eample: R = kω, T = 300 K B / f 4V / Hz rms = 4mV EE C45 ME C8 Fall 003 Lecture 3 (i a MHz badwidth) Thermal Noise (Cot.) Thermal oise curret: fid Norto equialet R Directio of arrow is arbitary R i i / f 4kBT = R Eample: R = kω, T = 300 K, BW = MHz 4k BT i = BW = 4µ A R EE C45 ME C8 Fall 003 Lecture 3 6

7 Resistor Noise i MEMS Itercoect resistace R it to capacitie positio sesors > routig i polysi 0 ca lead to a high resistaces, due to relatiely high sheet resistace of this layer > iertial MEMS ofte hae compliat suspesios large umber of squares i polysi ad sigificat cotributio to R it ( t) = Vˆ R R it C () X out R it C () ˆ ( t) = V EE C45 ME C8 Fall 003 Lecture 3 3 Flicker (/f) Noise Noise mechaism requires a DC curret, i cotrast to thermal oise Origi of /f oise i MOSFETs: surface states i = KI f a f Near DC, the oise curret dierges! EE C45 ME C8 Fall 003 Lecture 3 4 7

8 MOSFET Noise Sources Whe biased i saturatio, (V DS > V DS,sat ), the oise ca be represeted by a iput oise oltage ad a iput oise curret Origi of /f oise i MOSFETs: surface states i = 4kBT 3 g m f K f WLC o f f chael resistace i saturatio ierse depedece o gate area larger trasistors hae lower /f oise i i ω Cgs gm [4kBT f 3 gm KI f D f ] (eglectig DC gate curret ad it s shot oise) EE C45 ME C8 Fall 003 Lecture 3 5 MOSFET Noise Sources (Cot.) Equialet MOSFET smallsigal model with iputreferred oise sources i i i C gd C gs g m gs r o i d Crossoer frequecy betwee thermal ad flicker oise ca rage from khz to MHz EE C45 ME C8 Fall 003 Lecture 3 6 8

9 Buffer Equialet Iput Noise Substitute oise oltage ad curret for each MOSFET i buffer ad fid the total equialet oise at the iput i ( t) = Vˆ 4 g m6 = 4kBT f K flicker oise terms 3 gm g m R R it C () i R R it C () X out ( t) = Vˆ EE C45 ME C8 Fall 003 Lecture 3 7 Mechaical (Browia) Noise Impigig molecules gie rise to a Browia oise force: f = 4k Tb f B b = (Mω )/Q = dampig coefficiet Noise force applied to Mkb system results i radom Browia motio with a frequecydepedet power spectrum: = Implicatios: f << f ( 4kBTb / k) [ ( f / f ) ] f f Qf EE C45 ME C8 Fall 003 Lecture 3 8 9

10 Combiig Noise Sources If oise sources are ucorrelated, the their powers ca be added. For two oltage oise sources: = rms = = For a sesor, it is coeiet to refer all oise sources to the iput, by scalig them appropriately. For a capacitie diider positio sesor, the positio oise due to electroic oise at the iput of the buffer is:, = ˆ e V go V, e = go ˆ EE C45 ME C8 Fall 003 Lecture 3 9 SNR ad DR, Defied Sigaltooise ratio = SNR P = = s s s SNR = 0 log = 0 log 0 log 0 log P, Note : P oise is calculated oer a limited badwidth Note :,rms is take as the miimum detectable sigal, i the absece of special codig or sigal processig Dyamic rage = DR Ps,ma = s DR = 0 log 0 log P oise,ma = 0 log s,ma, rms s rms EE C45 ME C8 Fall 003 Lecture 3 0 0

11 Sigal ad Noise Waeforms Siusoid with amplitude ormalized to Gaussia oise with rms leel ormalized to ; ote that peakpeak oise leel is occasioally as high as 6! EE C45 ME C8 Fall 003 Lecture 3 SNR = ad 0 for Gaussia Noise EE C45 ME C8 Fall 003 Lecture 3