EE 435. Lecture 25. Data Converters

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1 EE 435 Lecture 5 Data Coverters

2 . Review from last lecture. Basic Operatio of CMFB Block V DD V FB V O1 V O CMFB Circuit V FB V OUT C L M 3 M 4 V OUT V IN M 1 M V IN C L V OXX CMFB Circuit V B M 9 V OXX CMFB Block V O1 Averager V AVG A V FB V O V +V V FB= 01 0 A s V OXX V OXX is the desired quiescet voltage at the stabilizatio ode (irrespective of where V FB goes)

3 . Review from last lecture. Commo-mode offset voltage V DD M 5 M 4 V O1 V 0XX V COFF V 0XX V O C 1 V B1 C M 1 M V C1 V C1 V YY M 3 Defiitio: The commo-mode offset voltage is the voltage that must be applied to the biasig ode at the CMFB poit to obtai the desired operatig poit at the stabilizatio ode

4 . Review from last lecture. Commo-mode gais V DD V DD M 5 M 4 V C M 4 V O1 C 1 V C1 V 0XX V 0XX V COFF V B1 M 1 M V C1 C V O V O V YY M 3 M V C1 M 3 V C3 V0 g 01+g 03 / ACOM - VC1 sc+g05 V0 gm5 ACOM - V sc+g V0 g m3 / ACOM3 - V sc+g C 05 C3 05 C g 01+g 03 / IT 1 ACOM0 - g I / g 05 m5 5 ACOM0 - T EB g 05 IT / VEB5 T I / V 4 IT / g / V m3 EB3 A COM30 = - g05 I T / VEB3 Although the commo-mode gai A COM0 is very small, A C0M0 is very large! Shift i V 0Q from V OXX is the product of the commo-mode offset voltage ad A COM0

5 . Review from last lecture. How much gai is eeded i the CMFB amplifier? VDD VFB V DD VOUT M3 M4 VOUT V C1 X V C3 M 4 M M 3 Y V C1 V O C V AVG V OXX A V FB VIN VIN M1 M CL VB M9 V =V 0UT-ACCEPTABLE COFF CL VOXX A 1-AA CMFB Circuit COM COM The CMFB Loop This does ot require a particularly large gai This is the loop that must be compesated sice A ad A COMP will be frequecy depedet Miller compesatio capacitor for compesatio of differetial loop will ofte appear i shut with C Ca create this half-circuit loop (without CM iputs o a fully differetial structure) for simulatios Results exted readily to two-stage structures with o big surprises Capacitaces o odes X ad Y create poles for CMFB circuit Reasoably high closed-loop CMFB badwidth eeded to miimize shifts i output due to high-frequecy commo-mode oise

6 . Review from last lecture. CMFB Circuits Several (but ot too may) CMFB circuits exist Ca be classified as either cotiuous-time or discrete-time V DD I B I B + V o - V o V OXX V 01 M 1 M M 3 M 4 V 0 N 1 N N C S C 1 C 1 C S N 1 V FB M 5 V SS V 01 V 0 N 1 N V FB N N 1 M 7 M 6 V SS

7 . Review from last lecture. CMFB Circuits Several (but ot too may) CMFB circuits exist Ca be classified as either cotiuous-time or discrete-time V DD I B I B V OXX I B + V o - V o V 01 M 1 M M 3 M 4 V 0 N 1 N C S C 1 C 1 C S N N 1 V FB M 5 V 01 V 0 N 1 N N N 1 V SS V FB M 7 M 6 V SS Circuit i blue ca be added to double CMFB gai

8 Types: Data Coverters A/D (Aalog to Digital) Coverts Aalog Iput to a Digital Output D/A (Digital to Aalog) Coverts a Digital Iput to a Aalog Output A/D is the world s most widely used mixed-sigal compoet D/A is ofte icluded i a FB path of a A/D A/D ad D/A fields will remai hot idefiitely techology advaces make data coverter desig more challegig embedded applicatios desigs ofte very applicatio depedet

9 D/A Coverters Basic structure: X IN DAC Basic structure with differetial outputs:: X IN DAC X + OUT X - OUT X + REF X - REF

10 D/A Coverters Notatio: DAC X IN DAC DAC

11 D/A Coverters DAC = b 0 is the Least Sigificat Bit (LSB) b -1 is the Most Sigificat Bit (MSB) Note: some authors use differet idex otatio A Ideal DAC is characterized at low frequecies by its static performace

12 D/A Coverters DAC = A Ideal DAC trasfer characteristic (3-bits) X - REF <0 0 0> <0 0 1> <0 1 0> <0 11> <1 0 0> <1 010> <1 1 0> <1 1 1> C 0 C 1 C C 3 C 4 C 5 C 6 C 7 Code C k is used to represet the decimal equivalet of the biary umber

13 D/A Coverters DAC = A Ideal DAC trasfer characteristic (3-bits) 7 8 C 0 C 1 C C 3 C 4 C 5 C 6 C 7

14 D/A Coverters DAC = A Ideal DAC trasfer characteristic (3-bits) X - REF C 0 C 1 C C 3 C 4 C 5 C 6 C 7 All poits of this ideal DAC lie o a straight lie

15 D/A Coverters X DAC IN C 0 C 1 C C 3 C 4 C 5 C 6 C 7 Most D/A ideally have a liear relatioship betwee biary iput ad aalog output Output represets a discrete set of cotiuous variables Typically this umber is a itegral power of, i.e. X is always dimesioless IN could have may differet dimesios A ideal oliear characteristic is also possible (waveform geeratio ad compadig) Will assume a liear trasfer characteristic is desired uless specifically stated to the cotrary

16 D/A Coverters X DAC IN C 0 C 1 C C 3 C 4 C 5 C 6 C 7 For this ideal DAC X X b b b b b OUT= b -j OUT=XREF j j=1 Number of outputs gets very large for large Spacig betwee outputs is / ad gets very small for large

17 D/A Coverters X DAC IN X LSB C 0 C 1 C C 3 C 4 C 5 C 6 C 7 Ideal steps all equal ad termed the LSB X LSB gets very small for small ad large e.g. If =1V ad =16, the N= 16 =65,536, X LSB =15.5μV

18 D/A Coverters X DAC IN A alterate ideal 3-bit DAC C 0 C 1 C C 3 C4 C5 C6 C7 Irrespective of which form is cosidered, the icremet i the output for oe Boolea bit chage i the iput is X LSB ad the total rage is 1LSB less tha

19 Applicatios of DACs Waveform Geeratio Voltage Geeratio Aalog Trim or Calibratio Idustrial Cotrol Systems Feedback Elemet i ADCs.

20 Waveform Geeratio with DACs Ramp (Saw-tooth) Geerator Period CLK Geerator -bit Biary Couter D/A A Example: For =3 t Example: For large t

21 Waveform Geeratio with DACs Sie Wave Geerator Period CLK Geerator -bit Biary or Couter D/A A m ROM RAM Example: For =3 t Distortio of the desired waveforms occurs due to both time ad amplitude quatizatio Ofte a filter precedes or follows the buffer amplifier to smooth the output waveform

22 A/D Coverters Basic structure: ADC Iput rage is Basic structure with differetial iputs/refereces: ADC X + IN ADC X - IN X + REF X - REF X + REF X - REF Iput rage is X + REF - X - REF Iput rage is (X + REF - X - REF)

23 A/D Coverters Notatio: ADC ADC ADC

24 A/D Coverters ADC =<d -1,d -,...d 0> d 0 is the Least Sigificat Bit (LSB) d -1 is the Most Sigificat Bit (MSB) Note: some authors use differet idex otatio A Ideal ADC is characterized at low frequecies by its static performace

25 A/D Coverters A Ideal ADC trasfer characteristic (3-bits) ADC =<d -1,d -,...d 0> C 7 <1 1 1> C 6 <1 1 0> C 5 <1 01> C 4 C 3 C C 1 C 0 <1 0 0> <0 11> <0 1 0> <0 0 1> <0 0 0> X LSB X LSB X = REF -X LSB

26 A/D Coverters A Ideal ADC trasfer characteristic (3-bits) ADC =<d -1,d -,...d 0> X LSB X = REF 7X LSB C 7 6X LSB C 6 5X LSB C 5 4X LSB 3X LSB C 4 C 3 X LSB X LSB C X LSB C 1 C 0 -X LSB The secod vertical axis, labeled,is the iterpreted value of

27 A/D Coverters ADC C 7 C 6 C 5 C 4 C 3 C C 1 C 0 For this ideal ADC X REF d-1 d- d-3 d1 d = -1 IN ε 4 8 X where ε is small (typically less tha 1LSB) d -j XREF = X j IN+ ε j=1 Number of bis gets very large for large Spacig betwee break poits is / ad gets very small for large ε is the quatizatio error ad is iheret i ay ADC

28 A/D Coverters ADC C 7 C 6 C 5 C 4 C 3 C C 1 C 0 Trasitio Poits X T1 X T X T3 X T4 X T5 X T6 X T7 Actual values of where trasitios occur are termed trasitio poits or break poits For a ideal -bit ADC, there are -1 trasitio poits Ideally the trasitio poits are all separated by 1 LSB -- X LSB = / Ideally the trasitio poits are uiformly spaced I a actual ADC, the trasitio poits will deviate a little from their ideal locatio Labelig Covetio: We will defie the trasitio poit X Tk to be the break poit where the trasitio i the code output to code C k occurs. This seemigly obvious orderig of break poits becomes ambiguous, though, whe more tha oe break poits cause a trasitio to code C k which ca occur i some oideal ADCs

29 A/D Coverters Quatizatio Errors ADC X T1 =X LSB C 7 C 6 C 5 C 4 C 3 C C 1 C 0 X LSB X LSB 3X LSB 4X LSB 5X LSB 6X LSB 7X LSB - ε Q X T1 X T X T3 X T4 X T5 X T6 X T7 Q X T1 X T X T3 X T4 X T5 X T6 X T7 -X LSB Magitude of ε Q bouded by X LSB for a ideal A/D

30 A/D Coverters Quatizatio Errors ADC Aother Ideal ADC C 7 X T1 =X LSB / C 6 C 5 C 4 C 3 C C 1 C 0 X LSB X LSB 3X LSB 4X LSB 5X LSB 6X LSB 7X LSB Q X - X OUT IN ε Q X T1 X T X T3 X T4 X T5 X T6 X T7.5 X LSB X T1 X T X T3 X T4 X T5 X T6 X T7 -.5 X LSB Magitude of ε Q bouded by ½ X LSB Is the performace of this ideal ADC really better tha that of the previous ideal ADC?

31 Data Coverter Architectures ADC DAC Large umber of differet circuits have bee proposed for buildig data coverters Ofte a dramatic differece i performace from oe structure to aother Performace of almost all structures are idetical if ideal compoets are used Much of data coverter desig ivolves idetifyig the problems associated with a give structure ad figurig out ways to reduce the effects of these problems Critical that all problems that are sigificat be idetified ad solved May of the problems are statistical i ature ad implicatios of ot solvig problems are i a yield loss that may be dramatic

32 Data Coverter Architectures ADC DAC Strategy for discussig data coverters Briefly look at some differet data coverter architectures Detailed discussio of performace parameters for data coverters More detailed discussio of data coverter architectures

33 Data Coverter Architectures ADC DAC Nyquist Rate Flash Charge Redistributio Pipelie Two-step ad Multi-Step Iterpolatig Algorithmic/Cyclic Successive Approximatio (Register) SAR Sigle Slope / Dual Slope Subragig Folded Iterleaved Over-Sampled (Delta-Sigma) Discrete-time First-order/Higher Order Cotiuous-time Curret Steerig R-strig Charge Redistributio Algorithmic R-R (ladder) Pipelied Subragig Discrete-time First-order/Higher Order Cotiuous-time

34 Data Coverter Architectures ADC Flash V REF V IN R R R R Thermometer to Biary Decoder R

35 Data Coverter Architectures ADC Successive Approximatio Register (SAR) C LK V IN V REF DAC DAC Cotroller

36 Data Coverter Architectures Charge Redistributio ADC V ICOMP C -1 C - C -3 C C -4 C C C C C C C 0 S 1 f A d-1 φb d-1 φb f f A d d -1 φb -1 φb A f A d- φb d - φ B f A d-3 φb d-3 φb f A d0 φb d 0 φ B f A φ B f A V IN V REF Successive Approximatio Block f A t 1 1 ' C C QSAM VIN Ci C 0 VIN V i INC i0 i0 1 C Q V d REDIS REF i i i0 f B d -1 VCOMP=0 T CONV t Q SAM Q REDIS d - T CLK VCOMP=1 VCOMP=0 t 1 C V d V C V REF i i IN i0 d 1 i IN VREF i i0 d 0 VCOMP=1 VCOMP=0 VCOMP=1 t t

37 Data Coverter Architectures Sigle Slope ADC R S R S C LK V REF Itegrator V OUT V IN V E E Biary Couter c Comparator Chages States whe t TR V I V dt I t V IN 0 REF 0 TR REF 0 V Couter stops whe VIN ttrvref I0 ; COUNT TCLK VREF I IN fclk 0 COUNT ; VREF I0 If calibrate so that f CLK I0 V ; IN V COUNT COUNT ; IN ; VREF V REF

38 Data Coverter Architectures DAC R-Strig V RFF R R S 1 S R V OUT R S N- R S N-1 S N is decoded to close oe switch

39 Data Coverter Architectures DAC Curret Steerig V RFF I 1 I I k S 1 S S k R V OUT

40 Data Coverter Architectures DAC R-R (4-bits) R R R R V OUT R R R R R d 3 d d 1 d 0 V REF By superpositio: d V =V d +V d +V d +V d = V V 3 4 k 4-k OUT REF 3 REF REF 1 REF 0 REF 4-k REF k k=0 k=1 d

41 Data Coverter Architectures Charge Redistributio DAC C -1 C - C -3 C C -4 C C C C C C C 0 S 1 f A f B d-1 φa d-1 φa f B d-1 φa d-1 φa f B d- φ d - φ A A f B d d-3 φ -3 φa A f B d0 φa d 0 φ A φ B f A f A V OUT V REF Successive Approximatio Block 1 Q V d C SET REF i i i0 1 1 ' C C QRDIS VOUT Ci C 0 VOUT V i OUTC i0 i0 f A t Q SET Q RDIS T CONV f B 1 C V d V C V REF i i OUT i0 d 1 i OUT VREF i i0 t

42 Performace Characterizatio of Data Coverters ADC DAC A very large umber of parameters ( ) characterize the static performace of a ADC! Ad eve more parameters eeded to characterize the dyamic performace of a ADC A large (but much smaller) umber of parameters are ivariably used to characterize a data coverter Performace parameters of iterest deped strogly o the applicatio Very small umber of parameters of iterest i may/most applicatios Catalog data coverters are geerally iteded to satisfy a wide rage of applicatios ad thus have much more striget requiremets placd o their performace Custom applicatio-specific data coverter will geerally perform much better tha a catalog part i the same applicatio

43 Ed of Lecture 5

EE 435. Lecture 25. Data Converters. Architectures. Characterization

EE 435. Lecture 25. Data Converters. Architectures. Characterization EE 435 Lecture 5 Data Coverters Architectures Characterizatio . eview from last lecture. Data Coverters Types: A/D (Aalog to Digital) Coverts Aalog Iput to a Digital Output D/A (Digital to Aalog) Coverts