EE 505. Lecture 14. Offset Voltages DAC Design

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1 EE 505 Lecture 14 Offset Voltages DAC Desig

2 Review from previous lecture: Cosider First Offset i Operatioal Amplifiers Iput-referred Offset Voltage: Differetial Voltage that must be applied to the iput to make the output assume its desired value Note: With a good desig, a desiger will have at the desired value if the compoets assume the values used i the desig Ay differece i the output from what is desired whe compoets assume the omial values used i a desig is attributable to a systematic offset voltage

3 Aalysis of Offset Voltage Review from previous lecture: but A AVT 0 ACox AL AW V T R C OXR L R W R WL WL WL WL W L C L W N OXN N N So the offset variace ca be expressed as L A AVT0 p 1 VTp0 V OS W1L 1 W1 L3 plw A A 1 1 p VEB 3 ACox AW AL L3W 1 W3L3 W1L 1 W3L3 W1L 1 W3 L3 W1 L1 W1L 1 W3L3 Ofte this ca be approximated by A 0 pl1 AVTp 0 plw A VT 1 1 p V V OS EB3 ACox W1L 1 W1 L3 L3W 1 W3L3 W1L 1 W3L3 W1L 1 Or eve approximated by L A AVT0 p 1 VTp0 V OS W1L 1 W1 L3 A

4 Offset Voltage Two types of offset voltage: Systematic Offset Voltage Radom Offset Voltage V ICQ Defiitio: The output offset voltage is the differece betwee the desired output ad the actual output whe V id =0 ad V ic is the quiescet commomode iput voltage. OFF = - VOUTDES Note: OFF is depedet upo V ICQ although this depedece is usually quite weak ad ofte ot specified

5 Offset Voltage V OFF V ICQ Defiitio: The iput-referred offset voltage is the differetial dc iput voltage that must be applied to obtai the desired output whe V ic is the quiescet commo-mode iput voltage. Note: V OFF is usually related to the output offset voltage by the expressio V V OUTOFF OFF= AC Note: V OFF is depedet upo V ICQ although this depedece is usually quite weak ad ofte ot specified

6 Offset Voltage Two types of offset voltage: Systematic Offset Voltage Radom Offset Voltage V ICQ After fabricatio it is impossible (difficult) to distiguish betwee the systematic offset ad the radom offset i ay idividual op amp Measuremets of offset voltages for a large umber of devices will provide mechaism for idetifyig systematic offset ad statistical Characteristics of the radom offset voltage

7 Systematic Offset Voltage Offset voltage that is preset if all device ad model parameters assume their omial value Easy to simulate the systematic offset voltage Almost always the desiger s resposibility to make systematic offset voltage very small Geerally easy to make the systematic offset voltage small Radom Offset Voltage Due to radom variatios i process parameters ad device dimesios Radom offset is actually a radom variable at the desig level but determiistic after fabricatio i ay specific device Distributio early Gaussia Has zero mea Characterized by its stadard deviatio or variace Ofte strogly layout depedet

8 Offset Voltage V OS Ca be modeled as a dc voltage source i series with the iput

9 Offset Voltage Effects of Offset Voltage - a example V IN R 1 R Desired I/O relatioship V DD V M t V IN

10 Effects of Offset Voltage - a example Desired I/O relatioship Offset Voltage V IN V DD R 1 R V M t Actual I/O relatioship due to offset V IN V DD V M t V IN V DD V M t V IN

11 Offset Voltage V OS V OS Effects ca be reduced or elimiated by addig equal amplitude opposite Dc sigal (may ways to do this) Widely used i offset-critical applicatios Comes at cosiderable effort ad expese Prefer to have desiger make V OS small i the first place

12 Effects of Offset Voltage Deviatios i performace will chage from oe istatiatio to aother due to the radom compoet of the offset Particularly problematic i high-gai circuits A major problem i may other applicatios Not of cocer i may applicatios as well

13 Offset Voltage Distributio umber Offset Voltage Bis Typical histogram of offset voltage (bied) after fabricatio

14 Offset Voltage Distributio Gaussia (Normal) pdf umber Offset Voltage Bis Typical histogram of offset voltage (bied) after fabricatio Mea is early 0 (actually the systematic offset voltage)

15 Offset Voltage Distributio umber Offset Voltage Bis Typical histogram of offset voltage (bied) i shipped parts Extreme offset parts have bee sifted at test

16 Offset Voltage Distributio umber Offset Voltage Bis Typical histogram of offset voltage (bied) i shipped parts Low-offset parts sold at a premium Extreme offset parts have bee sifted at test

17 Offset Voltage Distributio Pdf of zero-mea Gaussia distributio 0 x Characterized by its stadard deviatio σ or variace σ Offset voltage ofte specified as the 1σ or 3σ value

18 Offset Voltage Distributio Pdf of zero-mea Gaussia distributio f(x) -kσ kσ x Percet betwee: ±σ 68.3% ±σ 95.5% ±3σ 99.73%

19 Source of Radom Offset Voltages Cosider as a example: V DD R 1 R M 1 M I T V SS Ideally R 1 =R =R, M 1 ad M are matched IT = VDD - R Assume this is the desired output voltage

20 Source of Radom Offset Voltages Cosider as a example: V DD R 1 R M 1 M I T If everythig ideal except R =R +ΔR V SS IT = VDD - R+ R I V T OUT = - R

21 Source of Radom Offset Voltages Cosider as a example: V DD V DD R 1 R R 1 R M 1 M -V d / M 1 M V d / I T I T V SS V SS g A m V = - R

22 Source of Radom Offset Voltages Determie the offset voltage i.e. value of V X eeded to obtai desired output V DD R R+ΔR V X M 1 M g A m V = - R I T V SS I I V = - ΔR - A V T T OUT VDD- R V X -1 I V T X= ΔR A V

23 Source of Radom Offset Voltages Determie the offset voltage i.e. value of V X eeded to obtai desired output V DD R R+ΔR V X M 1 M I T g A m V = - R V SS -1 I V T X= A V ΔR IT IT ΔR IT ΔR ΔR V X= ΔR = VEB gmr gm R I T/VEB R R V = V X EB ΔR R

24 Source of Radom Offset Voltages The radom offset voltage is almost etirely that of the iput stage i most op amps V DD V DD V X M 3 M 4 V X M 3 M 4 V 1 M 1 M V S V V 1 M 1 M V V S I T I T (a) (b)

25 Radom Offset Voltages Bulk Source Gate Drai Bulk Source -chael MOSFET Gate Drai -chael MOSFET Impurities vary radomly with positio as do edges of gate, oxide ad diffusios Model ad desig parameters vary throughout chael ad thus the correspodig equivalet lumped model parameters will vary from device to device

26 Radom Offset Voltages V DD The radom offset is due to missmatches i the four trasistors, domiatly missmatches i the parameters {V T, μ,c OX,W ad L} V X M 3 M 4 The relative missmatch effects become more proouced as devices become smaller V 1 M 1 M V S V I T V Ti =V TN +V TRi C OXi =C OXN +C OXRi μ i =μ N +μ Ri W i =W N +W Ri L i =L N +L Ri Each desig ad model parameter is comprised of a omial part ad A radom compoet

27 Radom Offset Voltages V DD V Ti =V TN +V TRi V X M 3 M 4 C OXi =C OXN +C OXRi μ i =μ N +μ Ri V 1 M 1 M V S V W i =W N +W Ri I T L i =L N +L Ri For each device, the device model is ofte expressed as μn μri COXN COXRi W N+WRi L L I = V -(V V ) 1+ λ +λ V Di GSi TN TRi N Ri DS N Ri Because of the radom compoets of the parameters i every device, matchig from the left-half circuit to the right half-circuit is ot perfect This mismatch itroduces a offset voltage which is a radom variable

28 Radom Offset Voltages From a straightforward but tedious aalysis it follows that: A + A +A μ μ COX + A VTO μ W L W L W L W L p L V EB σ + A + VOS VTO p W L μ W L 4 p A L + +A w + W L W p L p L W L p W p p p p p p where the terms A VT0, A μ, A COX, A L, ad A W are process parameters V DD 1mV μ (-ch) AVT0 5mV μ (p-ch) A μ+a C OX.016μ (-ch).03μ (p-ch) V X M 3 M 4 A L=AW 0.017μ A VTO μ p L VOS W VTO p L μ W L p σ + A 3 Usually the A VT0 terms are domiat, thus the variace simplifies to V 1 M 1 M V S I T V

29 Correspodigly: Radom Offset Voltages V OS A W L VTO p L p W L A VTOp V EB 4 1 W L A L A 1 W L 1 W L p p 1 p A W L p p A A COX w L 1 W L 1 W L 1 W L p 1 p W p p which agai simplifies to A VTO μ p L VOS W VTO p L μ W L p σ + A V DD V X M 3 M 4 V 1 M 1 M V V S Note these offset voltage expressios are idetical! I T

30 Radom Offset Voltages Example: Determie the 3σ value of the iput offset voltage for The MOS differetial amplifier is a) M 1 ad M 3 are miimum-sized ad b) the area of M 1 ad M 3 are 100 times miimum size V DD V X a) A VTO μ p L VOS W VTO p L μ W L p σ + A μ p σ V A + A OS W VTO VTO p L μ 1 σ OS V σ V OS 7mV M 3 M 4 V 1 M 1 M V V S I T 3 σ 16mV V OS Note this is a very large offset voltage!

31 Radom Offset Voltages Example: Determie the 3σ value of the iput offset voltage for The MOS differetial amplifier is a) M 1 ad M 3 are miimum-sized ad b) the area of M 1 ad M 3 are 100 times miimum size V DD A VTO μ p L VOS W VTO p L μ W L p μ p σ A + A VOS W VTO VTO p L μ σ + A b) 1 σ VOS V X M 3 M 4 V 1 M 1 M V V S I T σ V OS 7.mV 3 σ 1.6mV V OS Note this is much lower but still a large offset voltage! The area of M 1 ad M 3 eeds to be very large to achieve a low offset voltage

32 Radom Offset Voltages V CC V CC Q 3 V X Q 4 Q 3 V X Q 4 V 1 Q 1 Q V V 1 Q 1 Q V V E V E I T I T (a) (b) It ca be show that V OS where very approximately A V J t + A E A = A = 0.1μ J Jp A A Jp Ep

33 Radom Offset Voltages V CC Example: Determie the 3σ value of the offset voltage of a the bipolar iput stage if A E1 =A E3 =10μ Q 3 V X Q 4 V OS AJ A V t + AE A Jp Ep V 1 Q 1 V E I T Q V V OS VA t J AE 1 5mV 0.1μ 1.6mV V OS 10μ 3 4.7mV V OS Note this value is much smaller tha that for the MOS iput structure!

34 Radom Offset Voltages Typical offset voltages: MOS - 5mV to 50MV BJT - 0.5mV to 5mV These ca be scaled with extreme device dimesios Ofte more practical to iclude offset-compesatio circuitry

35 Offset voltage difficult to determie i come classes of comparators V DD 1 1 M 13 M 5 M 6 M 14 V V 1 C 1 M 11 M 1 1 C 1 M 3 M 4 V IN M 7 M 8 V REF Dyamic clocked comparator Whe φ 1 is low, V 1 ad V are precharged to V DD ad o static power is dissipated Whe φ 1 is high, eters evaluate state ad o static power is dissipated

36 Offset voltage difficult to determie i come classes of comparators VDD Very small, very fast, low power 1 1 V C 1 M13 M5 M6 M11 M1 M14 1 V1 C1 But offset voltage ca be large (100mV or more) M3 M4 VIN M7 M8 VREF Dyamic clocked comparator H V 1 or V Metastable Output L V or V 1 CLK Trasitio Decisio is beig made shortly after clock trasitio whe devices are deep i weak iversio ad sigal levels are very small

37 Additioal details about offset voltage, statistical circuit aalysis, ad matchig ca be foud i the draft documet Statistical Characterizatio of Circuit Fuctios by R.L. Geiger

38 Summary of Offset Voltage Issues Radom offset voltage is geerally domiat ad due to mismatch i device ad model parameters MOS Devices have large V OS if area is small σ decreases approximately with Multiple figers for MOS devices 1/ offer A beefits for commo cetroid layouts but too may figers will ultimately degrade offset because perimeter/area ratio will icrease (A W ad A L will become of cocer) Offset voltage of dyamic comparators is ofte large ad aalysis ot straightforward Offset compesatio ofte used whe low offsets importat MOS: Bipolar: A VTO μ p L VOS W VTO p L μ W L p σ + A V OS AJ A V t + AE A Jp Ep

39 DAC Architectures Types Voltage Scalig Resistor Strig DACs (strig DACs) Iterpolatig Curret Steerig Biarily Weighted Resistors R-R Ladders Curret Source Steerig Thermometer Coded Biary Weighted Segmeted Charge Redistributio Switched Capacitor Serial Algorithmic Cyclic or Re-circulatig Pipelied Itegratig Resistor Switchig MDACs (multiplyig DACs)

40 DAC Architectures Structures Hybrid or Segmeted Mode of Operatio Curret Mode Voltage Mode Charge Mode Self-Calibratig Aalog Calibratio Foregroud Backgroud Digital Calibratio Foregroud Backgroud Dyamic Elemet Matchig Laser of Lik Trimmed Thermometer Coded or Biary Radix or o-radix Iheretly Mootoe

41 DAC Architectures Type of Classificatio may ot be uique or mutually exclusive Structure is ot mutually exclusive All approaches listed are used (ad probably some others as well) Some are much more popular tha others Popular Architectures Resistor Strig (iterpolatig) Curret Source Steerig (with segmetatio) May ew architectures are possible ad some may be much better tha the best curretly available All have perfect performace if parasitic ad matchig performace are igored! Major challege is i determiig appropriate architecture ad maagig the parasitics

42 Noideal Effects of Cocer Matchig Parasitic Capacitaces (icludig Charge ijectio) Loadig Noliearities Itercoect resistors Noise Speed Jitter Temperature Effects Agig Package stress

43 Observatios Yield Loss is the major pealty for ot appropriately maagig parasitics ad matchig ad this loss ca be ruthless The ultimate performace limit of essetially all DACs is the yield loss associated with parasitics ad matchig May desigers do ot have or use good statistical models that accurately predict data coverter performace If you work of a compay that does ot have good statistical device models Covice model groups of the importatc of dedvelopig these models (or) develop appropriate test strutures to characterize your process Existig oliear device models may ot sufficietly accurately predict device oliearities for high-ed data coverter applicatios

44 Observatios Experieced Desigers/Compaies ofte produce superior data coverter products Essetially all compaies have access to the same literature, regularly reverse egieer successful competitors products ad key beefits i successful competitors products are geerally ot locked up i patets High-ed desigs( speed ad resolutio) may get attetio i the peer commuity but practical moderate performace coverters usually make the cash flow Area (from a silico cost viewpoit) is usually ot the drivig factor i high-ed desigs where attractive price/mfg cost ratios

45 DAC Architectures X IN DAC X OUT R-Strig V RFF R X IN R S 1 S R R S N- R S N-1 S N X IN is decoded to close oe switch

46 DAC Architectures R-Strig V RFF X IN X IN DAC X OUT R R S 1 Biary to Thermometer Decoder S R R S N- R S N-1 S N Basic R-Strig DAC icludig Logic to Cotrol Switches

47 DAC Architectures X IN DAC X OUT Curret Steerig V RFF I 1 I I k X IN S 1 S S k R

48 DAC Architectures X DAC Curret Steerig IN X OUT X IN Biary to Thermometer Decoder (all ON) I 1 R S 1 I R S I N-1 R S N V REF 1 R F Iheretly Isesitive to Noliearities i Switches ad Resistors Smaller ON resistace ad less phase-shift from clock edges Termed bottom plate switchig Thermometer coded

49 DAC Architectures Curret Steerig X IN DAC X OUT V REF R X IN I S 1 S 1 I S 3 I 3 R R -1 R I S R F Biary-Weighted Resistor Arrays 1 Need for decoder elimiated! DNL may be a major problem INL performace about same as thermometer coded if same uit resistors used Sizig ad layout of switches is critical Observe thermometer codig ad biary weighted both offer some major advatages ad some major limitatios

50 DAC Architectures X IN DAC X OUT R-R (4-bits) R R R R R R R R R d 3 d d 1 d 0 V REF By superpositio: d V =V d +V d +V d +V d = V V 3 4 k 4-k OUT REF 3 REF REF 1 REF 0 REF 4-k REF k k=0 k=1 d

51 DAC Architectures Curret Steerig X IN DAC X OUT R-R V REF I R R R I R R R R I b 3 b 3 b b b 1 b 1 R F 1 R-R Resistor Arrays

52 DAC Architectures X IN Charge Redistributio DAC X OUT C F = C 1-1 C -1 C C C C X d -1 d -1 d - d - d 1 d 1 d 0 d 0 1A A 1 V REF T CLK 1 1A C X does some good thigs (mitigates V OS, 1/f oise ad fiite gai errors) Will ot cosider CX affects at this time A

53 DAC Architectures Charge Redistributio X IN DAC X OUT C -1 C - C -3 C C -4 C C C C C C C 0 S 1 A B d-1 φa d-1 φa B d-1 φa d-1 φa B d- φ d - φ A A B d d-3 φ -3 φa A B d0 φa d 0 φ A φ B A A V REF Successive Approximatio Block 1 Q V d C SET REF i i i0 1 1 ' C C QRDIS VOUT Ci C 0 VOUT V i OUTC i0 i0 A t Q SET Q RDIS T CONV B 1 C V d V C V REF i i OUT i0 d 1 i OUT VREF i i0 t

54 DAC Architectures X IN DAC X OUT MDAC MDAC D IN DAC D IN DAC V REF V REF fixed or limited rage V V D OUT REF IN DECIMAL V IN V IN Variable, ofte positive or egative V V D OUT IN IN DECIMAL

55 DAC Architectures X IN DAC X OUT Sigle Slope I REF V DD φ 1 Sample/Hold D IN CLK RST Timer/Couter C φ Divide by Sigle-Slope DAC

56 DAC Architectures X IN DAC X OUT Dual Slope D IN Timer/Couter CLK I REF1 φ 1 V DD φ I REF V SS C Sample/Hold Dual-Slope DAC CLK Divide by

57 Ed of Lecture 1

EE 435. Lecture 22. Offset Voltages Common Mode Feedback

EE 435. Lecture 22. Offset Voltages Common Mode Feedback EE 435 Lecture Offset Voltages Common Mode Feedback Review from last lecture Offset Voltage Two types of offset voltage: Systematic Offset Voltage Random Offset Voltage V ICQ Definition: The output offset