EE 435. Lecture 22. Offset Voltages

Transcription

1 EE 435 Lecture Offset Voltages

2 . Review from last lecture. Offset Voltage Definition: The input-referred offset voltage is the differential dc input voltage that must be applied to obtain the desired output when V ic is the quiescent common-mode input voltage. Note: V OFF is usually related to the output offset voltage by the expression V V OUTOFF OFF= D Note: V OFF is dependent upon V ICQ although this dependence is usually quite weak and often not specified

3 . Review from last lecture. Offset Voltage Two types of offset voltage: Systematic Offset Voltage Random Offset Voltage ICQ OUT fter fabrication it is impossible (difficult) to distinguish between the systematic offset and the random offset in any individual op amp Measurements of offset voltages for a large number of devices will provide mechanism for identifying systematic offset and statistical Characteristics of the random offset voltage

4 . Review from last lecture. Offset Voltage V OS Can be modeled as a dc voltage source in series with the input

5 . Review from last lecture. Offset Voltage OS OS Effects can be reduced or eliminated by adding equal amplitude opposite Dc signal (many ways to do this) Widely used in offset-critical applications Comes at considerable effort and expense Prefer to have designer make V OS small in the first place

6 . Review from last lecture. Offset Voltage Distribution Pdf of zero-mean Gaussian distribution Percent between: ±σ 68.3% ±σ 95.5% ±3σ 99.73%

7 . Review from last lecture. Source of Random Offset Voltages Determine the offset voltage i.e. value of V X needed to obtain desired output V X V DD R R+ΔR M 1 M V I T V SS -1 I V T X= ΔR V OUT IT IT ΔR IT ΔR ΔR V X= ΔR = = = VEB gmr gm R I T/VEB R R V = V X EB ΔR R g m V = - R

8 Source of Random Offset Voltages The random offset voltage is almost entirely that of the input stage in most op amps V DD V DD V X M 3 M 4 V X M 3 M 4 V OUT V OUT V 1 M 1 M V S V V 1 M 1 M V V S I T I T

9 Random Offset Voltages Bulk Source Gate Drain Bulk Source n-channel MOSFET Gate Drain n-channel MOSFET Impurities vary randomly with position as do edges of gate, oxide and diffusions Model and design parameters vary throughout channel and thus the corresponding equivalent lumped model parameters will vary from device to device

10 Random Offset Voltages The random offset is due to missmatches in the four transistors, dominantly missmatches in the parameters {V T, μ,c OX,W and L} The relative missmatch effects become more pronounced as devices become smaller V Ti =V TN +V TRi C OXi =C OXN +C OXRi μ i =μ N +μ Ri W i =W N +W Ri L i =L N +L Ri Each design and model parameter is comprised of a nominal part and random component

11 Random Offset Voltages V Ti =V TN +V TRi C OXi =C OXN +C OXRi μ i =μ N +μ Ri W i =W N +W Ri L i =L N +L Ri For each device, the device model is often expressed as ( μn+ μri)( COXN+ COXRi)( W N+WRi) ( + ) ( )[ ] L ( + L ) ( ) I = V -(V V ) 1+ λ +λ V Di GSi TN TRi N Ri DS N Ri Because of the random components of the parameters in every device, matching from the left-half circuit to the right half-circuit is not perfect This mismatch introduces an offset voltage which is a random variable

12 Random Offset Voltages From a straightforward but tedious analysis it follows that: μ μ COX + VTO n μ W L W L W L W L p L n V EB n σ = + + VOS VTO p WL n n μ nw nl 4 p L + + w + WL n n W p Lp Ln Wn Lp Wp n p n n p p n n p p where the terms VT0, μ, COX, L, and W are process parameters VT0 1mV μ 5mV μ (n-ch) (p-ch) μ+ C OX.016μ (n-ch).03μ (p-ch) L=W 0.017μ VTO n μp L n VOS W VTO p n Ln μn W n Lp σ + 3 Usually the VT0 terms are dominant, thus the variance simplifies to

13 σ Correspondingly: V OS = Wn L VTOn n μ + μ p n Random Offset Voltages L n n p W L VTOp V + 4 EBn 1 Wn L + n L μ n + 1 Wn L n 1 W L p p 1 + W L p μ p p + + w n 1 LnW COX 1 W L n 1 + n Wp Lp 1 + LpWp which again simplifies to VTO n μp L n VOS W VTO p n Ln μn W n Lp σ + V DD V X M 3 M 4 V OUT V 1 M 1 M V V S Note these offset voltage expressions are identical! I T

14 Random Offset Voltages Example: Determine the 3σ value of the input offset voltage for The MOS differential amplifier is a) M 1 and M 3 are minimum-sized and b) the area of M 1 and M 3 are 100 times minimum size V DD V X a) VTO n μp L n VOS W VTO p n Ln μn W n Lp M 3 M 4 σ + M 1 M μp σ V OS VTO n + W VTO p n Ln μn 1 σ OS 0.5μ 3 V σ V OS ( ) 7mV 3 σ 16mV V OS Note this is a very large offset voltage! V 1 V V S I T V OUT

15 Random Offset Voltages Example: Determine the 3σ value of the input offset voltage for The MOS differential amplifier is a) M 1 and M 3 are minimum-sized and b) the area of M 1 and M 3 are 100 times minimum size V DD VTO n μp L n VOS W VTO p n Ln μ n W n Lp μp σ VOS VTO n + W VTO p n Ln μn σ + b) 1 σ VOS 100( 0.5μ ) 3 V X M 3 M 4 V 1 M 1 M V V S I T V OUT σ V OS 7.mV 3 σ 1.6mV V OS Note this is much lower but still a large offset voltage! The area of M 1 and M 3 needs to be very large to achieve a low offset voltage

16 Random Offset Voltages It can be shown that σ V OS where very approximately V + = = 0.1μ Jn Jp Jn t En Jp Ep

17 Random Offset Voltages V CC Example: Determine the 3σ value of the offset voltage of a the bipolar input stage if E1 = E3 =10μ Q 3 V X Q 4 σ V OS V Jn t + En Jp Ep V 1 Q 1 V E I T Q V σ V OS V t J E 1 σ 5mV 0.1μ = 1.6mV V OS 10μ 3σ 4.7mV V OS Note this value is much smaller than that for the MOS input structure!

18 Random Offset Voltages Typical offset voltages: MOS - 5mV to 50MV BJT - 0.5mV to 5mV These can be scaled with extreme device dimensions Often more practical to include offset-compensation circuitry

19 Common Centroid Layouts Define p to be a process parameter that varies with lateral position throughout the region defined by the channel of the transistor. lmost Theorem: If p(x,y) varies linearly throughout a two-dimensional region, then p EQ = 1 p ( x,y) dxdy Parameters such at V T, µ and C OX vary throughout a two-dimensional region If a parameter varies linearly throughout a two-dimensional region, it is said to have a linear gradient.

20 y x p EQ = 1 p ( x,y) dxdy

21 Common Centroid Layouts lmost Theorem: If p(x,y) varies linearly throughout a two-dimensional region, then p EQ =p(x 0.y 0 ) where x 0,y 0 is the geometric centroid to the region. Parameters such at V T, µ and C OX vary throughout a two-dimensional region If a parameter varies linearly throughout a two-dimensional region, it is said to have a linear gradient. Many parameters have a dominantly linear gradient over rather small regions

22 (x 0,y 0 ) (x 0,y 0 ) is geometric centroid p EQ = 1 p ( x,y) dxdy If ρ(x,y) varies linearly in any direction, then the theorem states 1 p = p x,y dxdy = p x,y ( ) ( ) EQ 0 0

23 Common Centroid Layouts layout of two devices is termed a common-centroid layout if both devices have the same geometric centroid lmost Theorem: If p(x,y) varies linearly throughout a two-dimensional region, then if two have the same centroid, the parameters are matched! Note: This is true independent of the magnitude and direction of the gradient!

24 Recall parallel combinations of transistors equivalent to a single transistor of appropriate W,L W,L W,L W,L M 1 M M k kw,l W,L W,L W,L

25 Centroids of Segmented Geometries

26 Common Centroid of Multiple Segmented Geometries

27 Common Centroid of Multiple Segmented Geometries

28 Common Centroid Layouts Common centroid layouts widely (almost always) used where matching of devices or components is critical because these layouts will cancel all first-order gradient effects pplies to resistors, capacitors, transistors and other components lways orient all devices in the same way Keep common centroid for interconnects, diffusions, and all features Often dummy devices placed on periphery to improve matching!

29 Common Centroid Layout Surrounded by Dummy Devices

30 End of Lecture