Jitter Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And Applications

Transcription

1 Jitter Trasfer Fuctios For The Referece Clock Jitter I A Serial Lik: Theory Ad Applicatios Mike Li, Wavecrest Ady Martwick, Itel Gerry Talbot, AMD Ja Wilstrup, Teradye

2 Purposes Uderstad various jitter types (phase, period, ad cycle-to-cycle ad their relatioships Determie the appropriate jitter type for digital ad PLL based commuicatio liks (i.e., PCIe Figure out the jitter trasfer fuctios of referece clock ad trasmitter Suggest a appropriate ad accurate jitter test methodology for referece clock ad trasmitter for PCIe ad similar architectures

3 Outlie I. Review of serial data commuicatio architectur II. Jitter defiitios III. Jitter trasfer fuctios IV. System models V. Applicatio of the system models VI. Summary ad coclusios

4 I: Overview of Data Commuicatio

5 Covetioal Serial Data Commuicatio Architecture Tx Rx Medium Data D Q Data Clk CR/ PLL C Bit clock is embedded i the trasmittig data bits Bit clock is recovered via PLL at its Rx

6 Jitter Trasfer Fuctio I Covetioal Data Commuicatio Jitter i Rx: H rx (s Jitter + out H cr (s CR/ PLL - Differece fuctio at the sample flop Jitter trasfer fuctio is a high-pass

7 II: Defiitios

8 Uits Of Jitter Time ad Phase are used iterchageably to quatify jitter Time: Tideal Differece i time is: T = T T ideal measured Differece i phase is: Phase = 2π 2π T T measured ideal Phase: Tmeasured 2*pi The coversio is simply: T Phase = T ideal * 2π 2*pi * Tmeasured Tideal

9 Phase Jitter (Φ Also kow accumulated jitter 400 ps (2 π 200 ps Φ = T, = 1,2,, t Phase Jitter, s, (radias (π 0 ps (0 π -200 ps ( π -400 ps ( 2 π 1.6s 6.4s 8.0s 0s 3.2s 4.8s 9.6s T

10 Period Jitter The period Jitter (Φ is the differece betwee the measured period ad the ideal period ' = ( t t 1 T, = 1,2,, N Period Jitter (Φ Phase ad Period Jitter, s, (radias 400 ps (2 π 200 ps (π 0 ps (0 π -200 ps ( π Φ' ' Φ Also is: -400 ps ( 2 π Φ ' = Φ Φ 1 1.6s 3.2s 4.8s 6.4s 8.0s 9.6 T

11 Cycle-to-Cycle Jitter (Φ Cycle to cycle The differece betwee cosecutive bit periods '' = ( t t 1 ( t 1 t 2, = 1,2,, N Also is: '' ' ' = Φ Φ 1, = 1, 2,, N Phase, Period ad Cycle to Cycle Jitter, s, (radias 400 ps (2 π 200 ps (π 0 ps (0 π -200 ps ( π -400 ps ( 2 π Φ' Φ 1.6s 3.2s 4.8s 6.4s 8.0s 9.6s T Φ ''

12 Iterrelatioship i Time-Domai Phase Jitter Period Jitter Cycle-to-cycle Φ '' = ( Φ ' ' = ( Φ '' Cycle-to-cycle Period Jitter Phase Jitter Φ = Φ = Φ Differet represetatios of a same physical pheomea ' ''

13 Iterrelatioship i Frequecy-Domai 20 Various Jitter Measuremet Spectrum If ( Φ he period phase ( f cycle cycle ( ( f f = f c c f 2 c M a g i t u d e i d B Zeroth-Order Jitter Period Jitter Cycle-to-Cycle Jitter F r e q u e c y

14 Phase Jitter Measuremet ad Referece Clock Used Calculatig phase itter agaist a warped lock (or recovered lock reduces the mout of phase jitter alculated Phase Data phase Ref clock phase The amout of arpig depeds o he recovered clock s rasfer fuctio of the eceiver 0 Time Diff

15 Eye Closure/Total Jitter Modelig Give a clock ad data sigal V V ( t = V0 [ ω t P ( t] Clk Clk Clk + Eye closure P(t is the differece i the phase betwee the clock ad the data give by Clk ( t = V0 [ ω t P ( t] Data Data Data + Data P( t = P ( t P ( t clk data Eye closure direct depeds o the jitter trasfer fuctio of the receiver

16 III. Jitter Trasfer Fuctios

17 LTI System i Time-Domai A output sigal y(t equals to the iput sigal covolves with the impulse respose h(t y ( t = x ( τ h ( t τ dτ = Phase jitter is modeled as cotiuous sigal

18 LTI System i S-Domai S-domai fuctios is obtaied via Laplace trasformatio Y(s = X(sH(s y(t = Laplace -1 (Y(s Complex frequecy s ca be related to the real frequecy ω through s = jω, as doe i the models

19 LTI System Summary x(t X(s LTI System Time-domai: h(t S-domai: H(s y(t Y(s y ( t = h ( t * x ( t = x ( τ h ( t τ d τ Y ( s = H ( s X ( s H st ( s = h( t e dt

20 IV. System Models

21 Data Recovery Circuits (DRC Receiver Data Recovery is the essece of the system Traditioal Serial Commuicatio uses a PLL based Data Recovery PCI Express allows a less expesive digital based Data Recovery Circuit Usig phase iterpolator (PI, oversampled desig or digital cotrolled delay lie Majority implemeted DRCs are PIs

22 PLL Based DRC The system referece clock is ot used whe recoverig the data The Rx PLL eeds to track the trasmitter s jitter output Eye-closure/total jitter system model Referece Clock #1 X Trasmitte r Chip #1 Receiver i Chip #2 - f(x 1...x x 1 u 1 W1 D SET Q Y Eye Closure Data PLL x25 f(x 1...x x 1 u 1 CL R Q DRC PLL

23 Digital PI Based DRC Both Tx ad Rx use the referece clock Phase relatioship betwee ref clock ad data path matters Eye-closure/total jitter system model Trasmitter Chip #1 - Eye Closure Y Referece Clock X f(x 1...x x 1 u 1 W_1 D SET Q PLL x25 f(x 1...x x 1 PLL x25 u 1 W_2 f(x 1...x x 1 x 2 u 1 Phase Aligmet W_3 CLR Q Receiver i Chip #2

24 Phase/Jitter Trasfer Fuctio For A PLL The iput sigal to a PLL is V ( t P ( ( t = A si ω t i i i + where P i (t is the iput phase sigal ad is the state variable of the PLL The output from a PLL is V where P out (t is the output phase. The PLL has a phase trasfer respose h(t/h(s, they satisfy i ( t P ( ( t = A si ω t out out out + out P ( t h( t* P ( t out = i P ( s H( s P ( s out = i

25 Approximate Digital PI DRC Trasfer Fuctio The DRC Respose is modeled by a first order F_3dB high pass = 1.5 MHz This tracks the spread spectrum clock Mag (db Magitude of H3(s Trasfer Fuctio H 3 ( s s = s + ω Frequecy (Hz

26 Model For A PLL Trasfer Fuctio Ca be approximated by a 2d order trasfer fuctios for Rx ad Tx Some PLLs are 3 rd order or higher, additioal poles at higher frequecy do ot cotribute sigificatly to the eye closure H1( s = s 2 2sζω + 2sζω + ω 2 + ω ω 3 db = ω 1+ 2ζ + (1 + 2ζ + 1

27 System Trasfer Fuctio Models PLL Based DRC Model H_1(s f(x 1...x x 1 u 1 Clock Referece X(s f(x 1...x x 1 u 1 TX PLL W_1(s H_2(s f(x 1...x W_2(s - Y(s H t ( 1 H ( ( s = H ( s 2 1 s x 1 u 1 H_1(s Rx PLL Digital PI DRC Model f(x 1...x W_1(s x 1 u 1 f(x 1...x x 1 u 1 Clock Referece X(s TX PLL H_2(s f(x 1...x x 1 u 1 W_2(s - W_3(s f(x 1...x x 1 u 1 Phase Aligmet H_3(S Y(s H t ( 3 s = ( H1( s H2( s H ( s Rx PLL

28 Delay Model Delay trasfer fuctio models ito the system The phase delay is give by (L1 + L2 L3 This is modeled by exp(-s * t_delay Referece Clock L.1 Trasmitter Chip #1 f(x 1...x x 1 PLL x25 u 1 L.3 L.2 y_1 D SET Q f(x 1...x x 1 PLL x25 u 1 w_4 f(x 1...x x 1 x 2 u 1 Phase Aligmet y_2 CLR Q Receiver i Chip #2

29 Delay Trasfer Fuctio Example with 100 s 20 Delay 0 The trasfer fuctio has -20 ulls at the delay period -40 It has 6dB of gai at ½ -60 itervals of the delay -80 period -100 Doubles the effective jitter x 1 x y u 1 X Delay - Y Y = X[ 1 exp( s * t _ delay]

30 PLL Based Trasfer Fuctio PLL Based DRC does ot have delay depedecies PLL locks to the data rate ad wats a high Rx PLL respose for best performace H_1(s (x 1...x 1 u 1 Referece X(s f(x 1...x x 1 u 1 TX PLL W_1(s H_2(s f(x 1...x W_2(s - Y(s H t ( 1 H ( ( s = H ( s 2 1 s x 1 u 1 Rx PLL

31 Digital PI Based Trasfer Fuctio The differece fuctio icludes a arbitrary phase delay ot to exceed 30 s The delay ucorrelates the clock/data ad closes the eye This ca be estimated with 2X multiplier of H1(s- H2(s B (d M ag F1: 7.0e+006 F2: 2.2e+007 Trasfer Fuctios Mag -30 H1 H2-35 H1(delayed 30s - H2 2* (H1-H2 H Frequecy (Hz H t ( 3 s = 2 [ H1( s H 2( s] H ( s

32 V. Applicatios of System Models

33 Referece Clock Jitter Iduced Eye- Closure Estimatio Quatify system-level iterdepedecies Referece Clocks PLL parameters Calculate eye closure from the referece clock (most complex trasfer fuctio Usig previously defied models

34 PLL ad Digital PI Parameter Rages 1. The BW of the Tx ad RX PLLs is 1.5 MHz to 22 MHz, 3dB peakig maximum 2. The BW of the DRC (PI should be at least 1.5 MHz

35 X(s Models Applied to Measured Data: The iput spectrum ca be measured by measurig a clock ad applyig the jitter defiitios to get the phase jitter The phase jitter sigal is the trasformed ito the phase jitter spectrum, X(s H(s The models preseted here give Ht(s, the boudig fuctio, icludig the delay Y(s Y(s =X(sH(s Oe Method

36 Eye-Closure at The RX Sample Flop-O Method The iverse Laplace trasform of Y(s gives the eye closure i the time domai, y(t

37 Jitter Peakig ad Broadeig Differece fuctio domiated by Tx, Rx ad Phase Iterpolator PLL badwidth differece PLL peakig Referece clock oise spectrum as see at Tx ad Rx Ay oise uder the differece fuctio ca cause phase jitter 3 Dager Areas (7-22 MHz show Betwee A ad B ref clock jitter gets multiplied Left of A rolls off Right of B rolls off Chagig Tx, Rx below 7 MHz icreases width of dager areas Width ad Amplitude Impact varies with clock spectrum A B

38 VI. Summary ad Coclusio A quatitative mathematical relatioship betwee phase, period, ad cycle-to-cycle jitter is develope A geeric S-domai jitter trasfer fuctios for PCIe were established The jitter state variable is Phase Jitter, ad cycleto-cycle is ot the right merit for PCIe clock jitter Referece clock jitter trasfer fuctio is a ~(3th high-2th order low bad-pass Tx jitter trasfer fuctio is a 1 st order high-pass with a 3dB frequecy of 1.5 MHz The method developed here ca also be applied to ew ad relevat commuicatio architectures (i.e., FB DIMM, SATAII etc.