EE 505. Lecture 29. ADC Design. Oversampled

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1 EE 505 Lecture 29 ADC Desig Oversampled

2 Review from Last Lecture SAR ADC V IN Sample Hold C LK V REF DAC DAC Cotroller DAC Cotroller stores estimates of iput i Successive Approximatio Register (SAR) At ed of successive approximatio process, ADC output is i SAR Elimiates the power-cosumig amplifiers of the pipelied ADC Much slower tha pipelied ADC S/H at the iput is essetial Ca have excellet power performace Widely used structure with reewed attetio i recet years 2

3 Review from Last Lecture SAR ADC V IN Sample Hold CLK Does ot recover from errors Particularly problematic whe errors occur o earlier bits Over-rage protectio ca be added but at expese of additioal clock periods DAC V REF DAC Cotroller V IN V REF Output t V IN V REF Error o First Coversio Output t T CLK T CLK S/H Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 S/H S/H Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 S/H SOC EOC SOC EOC 3

4 Review from Last Lecture Alterate Charge Redistributio DAC SAR ADC V IN Sample Hold V REF C LK DAC DAC Cotroller V C 2-1 C 2-2 C 2-3 C 2C C C φ S φ S φ S φ S φ S φ S φ S DAC Cotroller V REF V IN Durig samplig phase, iput is sampled o all capacitors Durig successive approximatio process, capacitors are alterately coected to groud or V REF Voltage o commo ode will coverge to 0 Comparator is always comparig to groud thus reducig commo-mode oliearity errors Note iput sample is ot held idepedetly throughout the etire coversio process Bootstrapped switch is critical durig samplig phase Parasitic capacitaces o V C ode do ot affect fial output (Bottom plate) Major source of power dissipatio is i the charge redistributio process 4

5 Review from Last Lecture SAR ADC V IN Sample Hold C LK V REF Alterate Charge Redistributio DAC DAC DAC Cotroller C 1 C 2 C 3 C -1 C 2-1 C 2-2 C 2-3 C 2C C C φ S φ S φ S φ S φ S φ S φ S φx DAC Cotroller V REF V IN Durig redistributio, φ x =1 C 2 i i C 1 i Q SAMP 2 CV IN i 1 Q C d V V i i REF C i i i i REF C REF i C Q C2 dv V CV d 2 CV 2 i 1 i 1 i 1 i REF i C i 1 Q CV d 2 CV 2 1 5

6 Review from Last Lecture SAR ADC Alterate Charge Redistributio DAC V C 2-1 C 2-2 C 2-3 C 2C C C φ S φ S φ S φ S φ S φ S φ S DAC Cotroller V REF V IN i REF i 2 C IN i 1 CV d CV CV i 2 1 IN REF i 1 C i V V d V i IN REF i 2 C i V V d V 1 If the SAR output is adjusted so that VREF VREF VC 2 2 It follows that i VREF i V VREF di 2 VIN VREF di i1 i1 REF 6

7 Review from Last Lecture SAR ADC Charge Redistributio ADC with reduced charge redistributio eergy Goal: Oly switch if eeded!

8 Data Coverter Type Chart Oversampled Resolutio Nyquist 4 1K 10K 100K 1M 10M 100M 1G 10G Speed

9 Over-Sampled Data Coverters Geeral Classes Sigle-bit Multi-bit First-order Higher-order Cotiuous-time

10 Nyquist Rate T SIG t Samplig Clock

11 Over-Sampled Samplig Clock Effective Samplig Clock Quatizer Levels Effective Decimated Quatizer Levels Over-samplig ratios of 128:1 or 64:1 are commo Dramatic reductio i quatizatio oise effects Limited to relatively low frequecies

12 Recall: f SIG =50Hz f NYQ =100Hz f SAMP =2.3KHz Oversampled: 23:1 MatLab Results

13 Recall: Quatizatio Effects Simulatio eviromet: N P =23 f SIG =50Hz

14 Recall: Quatizatio Effects Res = 4 bits f SIG =50Hz f NYQ =100Hz f SAMP =1113KHz Oversampled: 11:1 E RMS X LSB 12

15 Recall: Quatizatio Effects Res = 10 bits f SIG =50Hz f NYQ =100Hz f SAMP =1113KHz Oversampled: 11:1 E RMS X LSB 12 Quatizatio oise is much lower but still sigificat

16 Recall: Quatizatio Effects Res = 10 bits f SIG =50Hz f NYQ =100Hz f SAMP =8904KHz Oversampled: 89:1 E RMS X LSB 12 Compared to the previous slide, it appears that the quatizatio oise has goe dow but really has t

17 Recall: Quatizatio Effects Res = 10 bits f SIG =50Hz f NYQ =100Hz f SAMP =8904KHz Oversampled: 89:1 E RMS X LSB 12 Ca ay additioal useful iformatio about the iput be obtaied sice we have may more samples tha are eeded?

18 Over-Samplig Res = 10 bits f SIG =50Hz f NYQ =100Hz f SAMP =8904KHz Oversampled: 89:1 X IN ADC X OUT E RMS X LSB 12 What would happe if we break the 4096 samples ito groups of 20 samples ad form? 20 1 Xˆ ( k 20 T ) x jt 20kT 20 OUT SAMP OUT SAMP SAMP j 1 Though the idividual samples have bee quatized to 10 bits, the arithmetic operatios will have may more bits The effective samplig rate has bee reduced by a factor of 20 but is still over 4 times the Nyquist rate Has the quatizatio oise bee reduced (or equivaletly has the resolutio of the ADC bee improved? Is there more iformatio available about the sigal? E RMS?

19 Over-Samplig X IN ADC Res = 10 bits E RMS Sice the quatizatio oise is at high frequecies, what would happe if filtered the Boolea output sigal? X OUT f SIG =50Hz f NYQ =100Hz f SAMP =8904KHz Oversampled: 89:1 X LSB 12 X IN ADC X OUT Digital Filter Y OUT =? E RMS? Y ( kt ) a x k jt m OUT SAMP j OUT SAMP j 0 Or m Y ( kt ) a x k jt b Y k jt OUT SAMP j OUT SAMP j OUT SAMP j0 j1 h

20 Over-Samplig Res = 10 bits f SIG =50Hz f NYQ =100Hz f SAMP =8904KHz Oversampled: 89:1 X IN ADC X OUT E RMS X LSB 12 Sice the quatizatio oise is at high frequecies, what would happe if filtered ad decimated the Boolea output sigal? Y ( kt ) a x k jt m OUT SAMP j OUT SAMP j 0 m Y ( kt ) a x k jt b Y k jt OUT SAMP j OUT SAMP j OUT SAMP j0 j1 h X IN ADC X OUT Digital Filter Y OUT =? Decimator Z OUT E? =? RMS

21 Over-Samplig X IN ADC X OUT E RMS X LSB 12 X X OUT Y OUT (mt SAMP ) IN ADC Slidig Averager =? E RMS? X IN ADC X OUT Digital Filter Y OUT =? Decimator Z OUT =? E RMS? What is the overhead? What is the performace potetial? How ca these or related over-samplig approaches be desiged? Though this approach may help quatizatio oise, will ot improve ADC liearity

22 Over-Samplig X IN ADC X OUT Digital Filter Y OUT =? f S =f SAMP OSR f S 2 1 f 0 X LSB fs 12 2 f 0 Quatizatio Noise 0.5f s f j T H e With ideal lowpass filter with bad-edge at f 0 V Qrms V LSB 12 1 OSR 1 f 0 0.5f s f For siusoidal iput with p-p value V REF SNR log( OSR) Improvemet of 3dB/octave or 0.5bits/octave X LSB fs 12 2 f 0 Quatizatio Noise 0.5f s f

23 Types of ADCs Over-sampled ΔΣ ADC (Delta-Sigma) CLK X IN Filter ADC 1 Decimator / Filter X OUT DAC Oversampled ADC Ati-aliasig filter at the iput (ot show), if eeded, to limit badwidth of iput sigal ADC is ofte simply a comparator CLK is much higher i frequecy tha effective samplig rate (maybe 128:1 though lower OSR also widely used) Ca obtai very high resolutio but effective samplig rate is small With clever desig, this approach ca reduce quatizatio effects ad improve liearity

24 Types of ADCs Over-sampled ΔΣ ADC (Delta-Sigma) CLK X IN Filter ADC 1 Decimator / Filter X OUT DAC Oversampled ADC Liearity performace almost etirely determied by the of DAC 1-bit DAC (i.e. oly a comparator for ADC) is iheretly liear ad widely used 20-bit liearity is achievable without ay trimmig usig 1-bit DAC Example: To obtai 16-bit liearity with a 10-bit DAC, the 10-bit DAC must be liear to at least the 16-bit level. This would usually require tedious trimmig of the DAC

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27 Removal of high-frequecy quatizatio oise But oise is still a problem i sigal bad 28

28 Noise reductio (oise shapig) i sigal bad 29

29 Noise reductio (oise shapig) i sigal bad 30

30 Noise reductio (oise shapig) i sigal bad 31

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33 SC Circuits ofte used for Modulator 34

34 Over-sampled ΔΣ ADC) Oversamplig Aloe: SNR log( OSR) 0.5 bits/octave Oversamplig ad First-Order Modulator: SNR log( OSR) 1.5 bits/octave Oversamplig ad Secod-Order Modulator: SNR log( OSR) 2.5 bits/octave 35

35 Noise reductio (oise shapig) i sigal bad 36

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42 Ed of Lecture 28

EE 505. Lecture 28. ADC Design SAR

EE 505. Lecture 28. ADC Design SAR EE 505 Lecture 28 ADC Desig SAR Review from Last Lecture Elimiatio of Iput S/H C LK X IN S/H Stage 1 r 1 Stage 2 r 2 Stage k r k Stage m r m 1 2 k m Pipelied Assembler (Shift Register