Slide Set Data Converters. Digital Enhancement Techniques

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1 0 Slide Set Data Converters Digital Enhancement Techniques

2 Introduction Summary Error Measurement Trimming of Elements Foreground Calibration Background Calibration Dynamic Matching Decimation and Interpolation

3 2 Introduction The rapid advancement of digital technology motivates an increasing use of digital techniques that improve the ADC or the DAC design by the correction or calibration of static and possibly dynamic limitations. The methods studied in this chapter can be classified into the following categories: Trimming of elements. Foreground calibration. Background calibration. Dynamic matching.

4 3 Error Measurement The basis of digital assistance methods is in the measurement of errors. F s A Error C C 2 C 3 LOGIC F s F e F e F s F s F e DAC V ref V ref Mesure of the mismatch between capacitors with extra DAC.

5 4 V A = V B C 2 C C + C 2 + C 3 () V A = V B(C 2 C ) + (V DAC + ɛ Q )C 3 C + C 2 + C 3 (2) (C 2 C ) max = V ref V B C 3 ; C mism = V B C 3. (3)

6 5 Off-line error mismatch of current sources. I ref V DD F R C _ V th Start LOGIC Error V AG + Stop COUNT I out, I out,2 F m, F, F,2 F m,i F i, F i,2 F m,n F N, F N,2 DI I u, I u,i I u,n Use of one extra current source and periodic error measurement of one element. T stop = k meas T ck = CV th I + δi u,i ; δi u,i = I ref I u,i (4)

7 6 Trimming of Elements Adjust a component value by discrete steps using fuses or anti-fuses that permanently open or close connections. MOS switches state is stored in a memory. Array of small elements, possibly binary weighted, connected in series or in parallel for connecting or disconnecting them according to a suitable control algorithm. Trimming suitably adapted to the design target and the algorithm used. The capacitor mismatch on a pipeline converter is critical in the first few stages. Some errors are acceptable other are not acceptable focus on the critical error.

8 7 V res = V N in C U,i V N Ref C U,ib i (5) C U,f ] ] N N V res = V in [N + ɛ i V DAC [k + ɛ i b i (6) F S C U, F R C U,f V IN F S C U, F R C U,f V IN F R F R F R F R V Ref F R, FR, F S F S F S V Ref F R, FR, F S F S F S F S C U,2 F R - + V RES F S C U,N F R - + V RES F R,2 FR, F S 2 F R,N F R, N F S F S C U,N F R F R C T F R F R,N F R, F S F S F S N (a) (b)

9 8 Trimming and measure of Offset - + S V os V os DAC UP/DOWN COUNTER DAC UP/DOWN COUNTER (a) (b) The measured offset is then used for a digital correction of results.

10 9 Foreground Calibration Trimming of elements or the mismatch measurement by a dedicated calibration cycle. Normally performed at power-on or during periods of inactivity of the converter. V in ADC ADDER OUT Calibration Signal DIGITAL LOGIC Memory Y out = Y C2 n c ( + ɛ k) + Y F ( + ɛ k ) Processing required to correct the interstage gain in a two-step converter. (7)

11 0 Foreground calibrated DAC IN ADDER Calibration Signal DAC V out Memory DIGITAL LOGIC ADC The ADC can be slow but must be precise.

12 Background Calibration Use of redundancy (one extra ADC or part of ADC) V in A N A L O G S E L E C T O R ADC ADC ADC ADC ADC D I G I T A L I N T E R F A C E ADDER OUT DAC Logic Memory

13 2 Background Calibration Use of two converters one fast and one slow. f s V in n-bit S/H ADC f s Addition OUT M ADC2 (n+p)-bit f s /M DIGITAL LOGIC Memory The slow converter determines the accuracy (it may provides more bit to have a more accurate correction of the INL)

14 3 Skip and fill method: replaces one out of a given number of input (p) samples with a test signal. The missing conversion is recovered by digital interpolation, for example, using an FIR filter. p=8 k k+... k+4... k+8... k+2... k+6 t The error power in the recovery process must be lower than the LSB ɛ 2 sk < p 2 2 2n; (8)

15 4 This method obtains the necessary room for background calibration by using a conversion rate higher than the sampling rate. The lower sampling frequency accommodates for n + conversions in n sampling periods, thus making the converter available one extra slot every n +. The shift between sampling and conversion times is managed by a queue block. Conversion t Sampling (a) t f s CAL f conv X Cal Queue M U X ADC OUT (b)

16 5 Gain and Offset in Interleaved Converters How to measure the Gain and offset mismatch? V in A N A L O G S E L E C T O R ADC ADC ADC ADC ADC D I G I T A L I N T E R F A C E ADDER OUT DAC Logic Memory Place the extra path, used as a reference, in parallel with one of the interleaved converters.

17 6 Assuming zero the offset and the gain of the reference path y ref (i) = x in (i) + ɛ Q,r (i) y p (i) = x in (i)δ G,i + O G,i + ɛ Q,p (i) y p (i) y ref (i) = x in (i)δ G,i + O G,i + ɛ Q,p (i) ɛ Q,r (i) (9) <y ref > M =<x in > M <y p y ref > M =<x in > M δ G,i + O G,i (0) A second average over another series of samples gives <y p y ref > N =<y ref > N δ G,i + O G,i () That makes a system of two equations with two unknowns δ G,i and O G,i.

18 7 Offset Calibration without Redundancy f f f f f V in A (a) V in f f ADC f f LOGIC OUT (b) Chopper stabilizer and spread-spectrum chopping.

19 8 Gain Calibration in Interleaved Converters X + S X+T Y' + Y ADC S + - T e G Y' X Y" S + - Y T DAC T SIG GEN z -k T' X DSP T' DSP X (a) (b) Addition of a test signal T to the input and subtraction after the A/D conversion. Signal processing enables calibration. Y = X( + δ G ) + T δ G + ɛ Q (2)

20 9 Digital gain mismatch correction for a two-channel time-interleave. The gain mismatch is equivalent to the multiplication of the input by a square-wave the output spectrum Y contains an image of the input at f N f in. X X 2 ADC ADC Y - 2 z + S + X 2 Y 2 f N /2 X X Y M Y DSP G /G 2 (a) Y Signal Y M Signal Amplitude Image Amplitude Chopping Image f in (b) f in -f N f N f f in f in -f N f N (c) f

21 20 Dynamic Matching Consider two nominally equal inter-changeable elements X and X 2. Assume X 2 = X ( + δ) and X + X 2 =. Y = 2 + δ or Y 2 = + δ 2 + δ (3) ɛ,2 = δ 2 + δ (4) The method is to use sequentially or randomly the elements X and X 2. With many elements the approach can be extended...

22 2 Dynamic matching of two elements I I 2 V R SW V R V B M M 2 I I 2 I out R R I ref (a) (b)

23 22 Example: Generation of a pseudo-random bit-stream (7-bit binary divided DAC) z - z - z - z - z - z - z - z - S n-bit n-bit Y PROC X if X > 2 n- ; Y=X - 2 n if X < -2 n- ; Y=X+ 2 n sign-bit

24 23 Butterfly Randomization Too many combinations of unity elements... M Sel Unity Element Y Thermometric Decoder R A N D O M I Z E R Sel Sel Sel Sel Sel Sel Sel Sel Sel Sel Sel Unity Element Unity Element Unity Element Unity Element Unity Element Unity Element Unity Element Unity Element Unity Element Unity Element Unity Element S Y out

25 B2 B B d i is the X i element flag. X = M Y (N) = M X i ; (5) M d i X i (6) ɛ Y (N) = M d i X i NX = M d i X i N M M X i. (7)

26 25 Assume the value of X i is X i = X + δx i (8) δx i is a random variable with variance X 2 σ 2 X. { } σy 2 = E [ɛ Y (N)] 2 = (N N 2 M )X2 σx 2 (9) which is is zero for zero or M elements, and has its maximum at N = M/2. The SNR determined by just the mismatch error and an OSR oversampling results SNR = 3M OSR σx 2 (20) With M = 8, OSR = (Nyquist-rate converter), δ = 0.002, the SNR = 65 db. If OSR = 32 SNR = 80 db.

27 26 Example 8.2 Use of the butterfly randomization in a 3-bit second order Σ Without randomization

28 27 With randomization Tones are transformed into white noise!

29 28 Individual Level Averaging The (ILA) approach aims at exercising each unity element with equal probability for each digital input code. Time-index In INDEXES I I 2 I 3 I 4 I I 6 I ELEMENT (a) Time-index In INDEXES I I 2 I 3 I 4 I I 6 I ELEMENT (b) Rotation or addition approach.

30 ELEMENT ELEMENT (a) time (b) time Use of elements with rotation and addition ILA (sequence )

31 30 Example 8.3 Use of ILA in the DAC of a 3-bit second order Σ. 60 PSD of the Mismatch Error (no DEM) 0 PSD of the Output PSD [db] PSD [db] Frequency [Hz] Frequency [Hz]

32 3 60 PSD of the Mismatch Error (ILA R, 8 elements) 0 PSD of the Output PSD [db] PSD [db] Frequency [Hz] Frequency [Hz]

33 32 60 PSD of the Mismatch Error (ILA A, 8 elements) 0 PSD of the Output PSD [db] PSD [db] Frequency [Hz] Frequency [Hz]

34 33 Data Weighted Averaging The method uses just one index, in common with all the input codes updated by the addition of the new input code to the content of the index register. U3 U4 U5 U INDEX U 2 U 3 U 2 U 4 S U U 5 U 0 U 6 U 9 U 8 U 7

35 34 Time-index INDEX In ELEMENT ELEMENT (a) (b) time DWA: Use of elements for a given input sequence.

36 35 The DWA method determines a first order shaping of the mismatch error. M δx i = 0 (2) i (k) = i+k i δx k for i + k < M i (k) = M δx k + i i+k M δx k for i + k > M (22) f s D k (nt) Cycle DAC + S + OUT k k 2 k 3 Cycle (a) k 3 k 4 k 5 (b) k 6

37 36 The noise injected in the first time-slot is (k ) = δx + δx 2 + δx 3 ; in the second time-slot is 2 (k 2 ) = δx 4 + δx 5 + δx 6 + δx 7. 3 (k 3 ) split in two parts 3 (k 3) = δx 8 and 3 (k 3) = δx + δx 2. that rearranged yields (k ) + 2 (k 2 ) + 3 (k 3) = 0 (23) 2 (k 2 ) = [ (k ) + 3 (k 3) ]. (24) (k ) [ (k ) + (k 3 ) ] z + (k 3 )z 2 (25) z (k )( z ) + 3 (k 3)( z ) (26) Similar considerations for the next clock periods obtain 4 (k 4 ), 5 (k 5 ) and the fraction of 6 (k 6 ) pertinent the second time slot. 4 (k 4 ) = [ 3 (k 3) + 5 (k 5 ) + 6 (k 6) ] (27) 4 (k 4 )z 2 [ 3 (k 3) + 5 (k 5 ) + 6 (k 6) ] z (k 5 )z (k 6)z 5 (28) [ z 5 (k 5 ) (k 3 )z 3] ( z ) + 6 (k 6)( z 2 ) (29)

38 37 The mismatch error passes through shaping function ( z d ), where d is the distance in clock-periods between the sample and the one almost halfway the considered cycle. ( z d ) d ( z ); z, (30) Smart Swiching n Logic D k (nt) 3 2 -z - IN DAC + S + OUT a smart switch directs the error to the proper amplification block before the ( z ) filter.

39 38 Comparing Butterfly and DWA Example PSD of the Mismatch Error (Butterfly with 8 elements) 0 PSD of the Output PSD [db] PSD [db] Frequency [Hz] Frequency [Hz]

40 39 60 PSD of the Mismatch Error (DWA with 8 elements) 0 PSD of the Output PSD [db] PSD [db] Frequency [Hz] Frequency [Hz]

41 40 Decimation and Interpolation The digital signal at the output of a Σ modulator removes the out-of-band shaped noise and reduces the clock-rate by decimation. The interpolation increases the sampling frequency and obtaining oversampling as required by a Σ DAC. Decimation Shaping leaves little noise in the signal band total aliased noise power much smaller than the in-band noise. V 2 F S 8 0 SNR/0 >> Hdec 2 (f 2 2L VF 2 S s/2) (3) 2 k 2 OSR for SNR = 04 db L = 3, OSR = 32 and k = 8, stop-band gain much lower than 87 db.

42 4 With large decimation factors the operation in done in successive steps. Decimation factor K D (K D = 2 k d ) is divided into the product K D = 2 k d 2 k d2 2 k dp, (32) Possible architecture f s f s /M f s /(M M 2 ) f s /(M M 2 M 3 ) f s /(M M 2 M 3 ) M n-th SINC FILTER M 2 FIR half-band M 3 FIR half-band DROP CORRECTION M =4-32 M 2 =2-8 M 3 =2-4

43 42 Y sinc (n) = N N 0 X(n i). (33) H s (z) = N N 0 z i = N z N ; (34) z Sinc Magnitude Response Amplitude [db ] sinc 3 sinc sinc f/f s

44 43 A sinc filter attenuates only at the required frequencies but the attenuation must ensuring the desired noise rejection. For an L-th order modulator it is required using a sinc L+ filter. For example, a sinc filter is not an adequate for a first order Σ. The spectrum of the quantization noise, shaped by ( z ) 2 and filtered by Hn 2 (z), is vn,out 2 (z) = v2 n,q ( z ) 2 [ ] z N 2 = v2 n,q N 2 z N ( 2 z N ) 2. (35) The use of the z e jωt transformation obtains [ vn,out 2 (ω) = v2 n,q 2 sin(nωt/2) ] 2 (36) N using sin(nωt/2) ± NωT/2 v 2 n,out (2πf) = v2 n,q [2πfT ] 2 (37) H s (z) = ( + z + z 2 + z 3 ) 3 (38)

45 44 The sinc L+ filter is a transversal structure. For example for L = 3 and N = 4 the filter is = + 3z +6z 2 +0z 3 +2z 4 +2z 5 +0z 6 +6z 7 +3z 8 +z 9 The coefficients can be stored in a memory or generated step by step during the filtering operation. For large values of N the number of coefficients and the number of taps of the transversal filter can become impractical. A possible alternative architecture is Integrators IN S REG S REG S REG N S S S OUT REG REG REG Differentiators

46 45 Interpolation Single stage is practical only for for relaxed transitions between pass-band and stop band. A transition region f s with more than 00 db of attenuation in the stop band and a ripple of about db in the pass band requires a 25 taps FIR filter. 20 Magnitude Response 0!20!40 Amplitude [db]!60!80!00!20!40!60! f/f s

47 46 2f s 4f s 8f s 64f s (28f s ) (6) FIR FIR2 FIR3 S&H taps taps 4-6 taps Magnitude Response FIR Magnitude Response FIR Amplitude [db] f/f s Magnitude Response FIR f/f s Magnitude Response S&H 0 20 Amplitude [db] f/f s f/f s

48 47 Wrap-up The use of digital techniques improves the data converter performances. The static accuracies are improved by measuring the error or by calibrating elements. We have seen various approaches for obtaining the results. The foreground calibration requires a specific time-period during which the converter in not used. Background calibration is more complex as it is done while the converter works normally. We have seen that calibration can be very expensive and it is worth to limit the correction to the critical limits (for example, gain error or offset can be acceptable). The dynamic matching of elements is appropriate for sigma-delta modulators, especially when they grant a shaping of the mismatch error. Digital techniques are necessary for the pre and the post-processing of data. Low-pass filtering, decimation and interpolation have been briefly discussed. More details are found on specific courses on digital signal processing.

Oversampling Converters

Oversampling Converters David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 56 Motivation Popular approach for medium-to-low speed A/D and D/A applications requiring