SWITCHED CAPACITOR AMPLIFIERS

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1 SWITCHED CAPACITOR AMPLIFIERS AO 0V 4.

2 AO 0V 4.2

3 i Q AO 0V 4.3

4 Q AO 0V 4.4

5 Q i AO 0V 4.5

6 AO 0V 4.6

7 i Q AO 0V 4.7

8 Q AO 0V 4.8

9 i Q AO 0V 4.9

10 Simple amplifier First approach: A 0 = infinite. C : V C = V s V x V CF = 0 V out = V x : V C = V s V s V x = V x because V s = V s Q v = Q/C Q V [ V CF x ( V s V x )]C = = = C V out = V x V CF = V s V C x F V s C Alternatively: φ: φ2: V C = V x V CF = 0 V out = V x V s (alt: ) C Q CF V C Q V CF = = = V s V x [ V s V x ( V x )]C (alt: ) V x V o C V out = V s V C x F Amplifier offset AO 0V Ref.: Unbehauen 4.0

11 Summing amplifier (ideal): V out = p n [ V ( φ ) V ( φ2 )] C p n [ V C 2φ V 2φ2 ] C 2 V F C x F ktt/2 Generally: V out ( kt) = m C j p V x T V C j kt F 2 V n ( kt ) j j = (4.) V p C kt V o V n V 2 p C 2 V x V 2 n v j C j v j C j v m C m AO 0V Ref.: Unbehauen 4.

12 Effect of Parasitics Final amplifier open loop gain (DC) Input offset Leak current from sampling capacitors. Parasitic capacitance (conductors) Final gain V s C V i A V out The result is found by applying the super position method on the output signal. That is the sum of all effects. I L C p Parasitc components V x AO 0V 4.2

13 Output signal as a consequence of offset and final gain. Open loop gain: A V out0 = ( V x V out0 )A ( A )V out0 = V x A V out0 A = V A x = ε 0 V x (4.2) V i_o A V out0 V x AO 0V Ref.: Unbehauen 4.3

14 Output signal as a consequence of final gain and parasitic capacitance. V out = V i A V s = v s : A A V C = V s V i = V s V x V A CF = 0 V out = V x A (incremental voltage changes): C C v i v s F = v C C p C out F C C p v s C v i A C p v out C C v out = v i A v s A F = v C C p C out A F C C p C v out A = Av C C p C s F C C p v out C Av s C C p C = F = A C C p Av s C C C p A C v out C v A C ( = = v F ( C C p ) A s C s ε A C p C ) = F ε A A (4.3) AO 0V Ref.: Unbehauen 4.4

15 Output signal as a consequence of leak current I L in the pulse period τ. C C p I v outl L τ = = C F ε C C p A I L τ ( ε A ) = I L τa C C p ( A) (4.4) τ v s C v i A v out I L C p V x AO 0V Ref.: Unbehauen 4.5

16 Final result Summing (4.2), (4.3) and (4.4): C I v out v L τ AV = ε s x A ( ε A ) A (4.5) AO 0V Ref.: Unbehauen 4.6

17 Offset Compensation : V x is sampled, is charged to V x : When Q= V s C is transferred to, V x is already across with the negative charge at the amplifier output (when V x er positive) : V C = V s V x V CF = V x V out = V x : V C Q V CF = V C x = F = ( V s V ) V x s = V x [ V x ( V s V x )]C V C x F C C V out V x V s = V C x = V s F v s C V x v o AO 0V Ref.: Unbehauen 4.7

18 Compensation of charge injection: Add dummy switches that are clocked in anti phase with the real switches. L φ L φ L φ W/2 W W/2 Compensation of charge injection and clock feed through: Introduce corresponding switches and capacitance on both amplifier s input terminals. v p v n v k p C C k v o v n k φ 2 C C k AO 0V Ref.: Unbehauen 4.8

19 Dynamical Properties of SC Amplifiers g m : Amplifier transconductance, determined by the transconductance of the input transistors. r o : Amplifier output resistance C L : Load capacitance of the configuration. C p : Parallel capacitance of the input node g m r o C L = C o C o G g m r o 3 db v v o 0.63v o C p g m r o C o [db] /τ =/r o C L C L = C o ( C p )/( C p ) C p / τ= t t C /r o C L C g m r o C o 0 log ω C n n C L2 = C o Σ C i /r o C L2 g m /C L AO 0V 4.9

20 Requirements on the time constant: v o = v oss, ( e t τ ) dv o dt t = 0 = v oss, e t τ = τ t = 0 v oss, τ v o,ss v o v o,ss Settling to % of v o,ss set the following requirement to t s : t s e t s τ = 0,0 = ( τ) ln0,0 = 4,6τ τ t s t τ = t s 46, AO 0V 4.20

21 Instrumental Amplifiers Correlated double sampling Phase : Offset and LF noise are stored at the input Phase 2: Subtracted from the amplified signal. 2 Differential topology Reduces charge injection and clock feed through. Reduces non linearity in capacitors (distortion) Improves PSSR (Power Supply Rejection Ratio) v i v i 2 C 2 2 C * Semidifferential * v o v i v i 2 C C * * v o v o = (v i v i ) C / AO 0V 4.2

22 READOUT CHAIN ARCHITECTURE AO 0V 4.22

23 Column read out (principle) AO 0V 4.23

24 Column read out (cont.) rst SHS 2() rad 2 v o nt nt t 2(n) 2 2 I bias 2 2(n) 2 v o 2 ADC SHR * 2 AO 0V 4.24

25 Read out time diagram Pixel output Pixel reset Sample signal Sample reset Amplifier reset () Transfer (2) Column Column n Column n ADC strobe AO 0V 4.25

26 Column parallel read out (example) Slow ADC is OK: Successive Approximation Single slope (common to all columns) Cyclic Vdd Row select Reset Strobe Address (Slope) ADC ADC ADC Data bus AO 0V 4.26

27 Synchronizing Mechanical shutter Synchronized with ERS Mechanical shutter Synchronized with Global Reset AO 0V 4.27

28 Synchronizing (cont.) Electronic global shutter AO 0V 4.28

29 Reduced resolution but higher frame rates Skipping Simple solution Aliasing Binning Spatial LP filter More complex AO 0V 4.29

30 References: Unbehauen: MOS SwitchedCapacitor and ContinuousTime Integrated Circuits and Systems Rolf Unbehauen, Andrzej Cickocki SpringerVerlag Nakamura: Image Sensors and Signal Processing for Digital Still Cameras, edited by Junich Nakamura Taylor & Francis AO 0V 4.30

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