EXAMPLE DESIGN PART 1

Transcription

1 ECE37 Advanced Analog Circuits Lecture 3 EXAMPLE DESIGN PART Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca

2 Course Goals Deepen understanding of CMOS analog circuit design through a top-down study of a modern analog system a delta-sigma ADC Develop circuit insight through brief peeks at some nifty little circuits The circuit world is filled with many little gems that every competent designer ought to know. ECE37 3-2

3 Date Lecture (M 3:00-5:00) Ref Homework RS MOD & MOD2 ST 2, 3, A : Matlab MOD& RS 2 MODN + Σ Toolbox ST 4, B 2: Σ Toolbox RS 3 Example Design: Part ST 9., CCJM 4 3: Sw.-level MOD RS 4 Example Design: Part 2 CCJM TC 5 SC Circuits R 2, CCJM 4 4: SC Integrator TC 6 Amplifier Design Reading Week No Lecture TC 7 Amplifier Design 5: SC Int w/ Amp RS 8 Comparator & Flash ADC CCJM TC 9 Noise in SC Circuits ST C RS 0 Advanced Σ ST 6.6, 9.4 Project TC Matching & MM-Shaping ST , TC 2 Pipeline and SAR ADCs CCJM 5, Exam Proj. Report Due Friday April Project Presentation ECE37 3-3

4 Highlights (i.e. What you will learn today) MOD2 implementation 2 Switched-capacitor integrator Switched-C summer & DAC too 3 Dynamic-range scaling 4 kt/c noise 5 Verification strategy ECE37 3-4

5 Review: A Σ ADC System desired signal f B shaped noise f B f B f s 2 f s 2 Nyquist-rate PCM Data U Σ Modulator V Digital Decimator W U Loop Filter Y DAC V(z )= STF(z )U(z )+ NTF(z )E(z ) STF(z ): signal transfer function NTF(z ): noise transfer function E(z ): quantization error E V ECE37 3-5

6 U z Review: MOD E Vz ( ) = NTF( z)ez ( ) + STF( z)uz ( ) Q NTF( z) = ( z ) STF( z) = z NTF ( e j 2πf ) ω 2 for ω « Normalized Frequency (f /f s ) Doubling OSR improves SQNR by 9 db Peak SQNR dbp( 9 OSR 3 ( 2π 2 )); dbp( x) 0log 0 ( x) ECE37 3-6

7 U z z Review: MOD2 z Q E V NTF( z) = ( z ) 2 STF( z) = z NTF ( e j 2πf ) ω 4 for ω « Normalized Frequency (f /f s ) Doubling OSR improves SQNR by 5 db Peak SQNR dbp( ( 5 OSR 5 ) ( 4π 4 )) ECE37 3-7

8 dbfs/nbw Review: Simulated MOD2 PSD 0 Input at 50% of FullScale OSR = 28 Simulated spectrum (smoothed) 40 db/decade Theoretical PSD (k = ) NBW = Normalized Frequency (f /f s ) ECE37 3-8

9 Review: Advantages of Σ ADC: Simplified Anti-Alias Filter Since the input is oversampled, only very high frequencies alias to the passband. A simple RC section often suffices. If a continuous-time loop filter is used, the anti-alias filter can often be eliminated altogether. DAC: Simplified Reconstruction Filter The nearby images present in Nyquist-rate reconstruction can be removed digitally. + Inherent Linearity Simple structures can yield very high SNR. + Robust Implementation Σ tolerates sizable component errors. ECE37 3-9

10 Let s Try Making One! Clock at f s = MHz. Assume BW = khz. OSR = f s ( 2 BW ) = MOD: SQNR 9 db/octave 9 octaves = 8 db MOD2: SQNR 5 db/octave 9 octaves =35 db Actually more like 20 db. SQNR of MOD is not bad, but SQNR of MOD2 is awesome! In addition to MOD2 s SQNR advantage, MOD2 is usually preferred over MOD because MOD2 s quantization noise is more well-behaved. ECE37 3-0

11 What Do We Need? E U z z z Q V Summation blocks 2 Delaying and non-delaying discrete-time integrators 3 Quantizer (-bit) 4 Feedback DACs (-bit) 5 Decimation filter (not shown) Digital and therefore easy. ECE37 3-

12 Switched-Capacitor Integrator Single-ended circuit: φ C Vin φ2 φ2 φ C2 φ Vout z Timing: Vin φ φ2 φ v in ( n) v in ( n + ) φ2 Vout v out ( n) v out n + Time ( ) ECE37 3-2

13 φ: q 2 ( n) = C 2 V out ( n) q ( n) = C V in ( n) Vin Vout φ2: q 2 n + q 0 ( ) = q 2 ( n) + q ( n) Vin Vout ECE37 3-3

14 q 2 ( n + ) = q 2 ( n) + q ( n) zq 2 ( z) = Q 2 ( z) + Q ( z) Q 2 ( z) Q ( z) z This circuit integrates charge Since Q = C V in and Q 2 = C 2 V out V out ( z) V in ( z) Note that the voltage gain is controlled by a ratio of capacitors With careful layout, 0.% accuracy is possible. = = C C z ECE37 3-4

15 Summation + Integration V φ φ2 C φ2 φ C φ Vout z φ C2 V2 φ2 V out ( z) = C C V C ( z) V C 2 ( z) ( z ) Adding an extra input branch accomplishes addition, with weighting ECE37 3-5

16 b DAC + Summation + Integration V φ φ2 C φ2 φ C φ Vout z DAC v +Vref Vref φ v φ v φ2 C2 ECE37 3-6

17 Differential Integrator C2 φ C φ2 φ Vin φ2 φ Vout Allows V in,cm (= V out,cm of previous stage) to be arbitrary φ C φ2 φ ECE C2 CM of amplifier inputs Amplifier drives only capacitors, so a high output impedance is OK

18 Non-Delaying Integrator Single-ended circuit: Swap Phases C2 Vin φ φ2 C φ φ2 φ Vout Timing: φ φ2 φ φ2 Vin v in ( n) v in ( n + ) Vout v out ( n) v out n + ( ) Integration occurs during φ ECE37 3-8

19 φ2: q = 0 q 2 ( n) = C 2 V out ( n) Vin Vout φ: q 2 ( n + ) = q 2 ( n) q ( n + ) Vin q ( n + ) = C V in ( n + ) Vout ECE37 3-9

20 q 2 ( n + ) = q 2 ( n) q ( n + ) zq 2 ( z) = Q 2 ( z) zq ( z) Q 2 ( z) Q ( z) = z z V out ( z) V in ( z) C C 2 z z Delay-free integrator (inverting) = ECE

21 Half-Delay Integrator Single-ended circuit: φ C Vin φ2 φ2 φ C2 φ2 Sample output on φ2 Vout Timing: Vin φ φ2 φ v in ( n) v in ( n + ) φ2 Vout v out ( n) v out n + Time ( ) ECE37 3-2

22 Half-Delay Integrator Output is sampled on a different phase than the input z 2 / Some use the notation Hz ( ) = to denote the shift in sampling time z I consider this an abuse of notation. An alternative method is to declare that the border between time n and n+ occurs at the end of a specific phase, say φ2 A circuit which samples on φ and updates on φ2 is non-delaying, i.e. Hz ( ) = z ( z ), whereas a circuit which samples on φ2 and updates on φ is delaying, i.e. Hz ( ) = ( z ). ECE

23 Timing in a Σ ADC The safest way to deal with timing is to construct a timing diagram and verify that the circuit implements the desired difference equations E.g. MOD2: un ( ) x ( n + ) x 2 ( n + ) x ( n) z - z - x 2 ( n) vn ( ) Q Difference Equations: v( n) = Qx ( 2 ( n) ) x ( n + ) = x ( n) vn ( ) + un ( ) x 2 ( n + ) = x 2 ( n) vn ( ) + x ( n + ) (0) () (2) ECE

24 Switched-Capacitor Realization 2 2 x 2 2 x 2 v Reference feedback shares input/interstage capacitor Timing 2 x (n) x (n+) 2 x 2 (n) 2 x 2 (n+) 0 v(n) Timing looks OK! ECE

25 Signal Swing So far, we have not paid any attention to how much swing the op amps can support, or to the magnitudes of u, V ref, x and x 2 For simplicity, assume: the full-scale range of u is ± V, the op-amp swing is also ± V and V ref =V We still need to know the ranges of x and x 2 in order to accomplish dynamic-range scaling ECE

26 Dynamic-Range Scaling In a linear system with known state bounds, the states can be scaled to occupy any desired range e.g. one state of original system: α β α z x 2 β 2 state scaled by /k: α k kβ α 2 k z x k k β 2 ECE

27 State Swings in MOD2 U Linear Theory z z X X 2 z Q E V V = z U + ( z ) 2 E z X = ( z U V ) = U ( z )E X 2 = V E = z U + ( 2z + z 2 )E If u is constant and e is white with power σ2 e = 3, then x = u, σ 2 x = 2σ2 = 2 3, e x 2 = u and σ 2 x = 5σ2 = 5 3 e 2 ECE

28 ρ x Simulated Histograms mean = 0.0 sigma = 0.67 u = ρ x 2 mean = 0.4 sigma = u = ρ x mean = 0.70 sigma = ρ x 2 mean =.5 sigma = ECE

29 Observations The match between simulations and our linear theory is fair for x, but poor for x 2 x s mean and standard deviation match theory, although x s distribution does not have the triangular form that would result if e were white and uniformly-distributed in [,]. x 2 s mean is 50-00% high, its standard deviation is ~25% low, and the distribution is weird. Our linear theory is not adequate for determining signal swings in MOD2 No real surprise. Linear theory does not handle overload, i.e. where x, x 2 when u >. Is there a better theory? Yes, but it is complicated and gives minimal insight. ECE

30 MOD2 Simulated State Bounds 0 8 x ( 5 u ) ( u ) x 6 4 analytic bounds x u simulation ECE u

31 Scaled MOD2 Take x = 3 and x 2 = 9 The first integrator should not saturate. The second integrator will not saturate for dc inputs up to 3 dbfs and possibly as high as dbfs. Our scaled version of MOD2 is thus U z X X 2 /3 /3 z z 9 Q V /3 /9 Omit since sgn(ky ) = sgn(y ) ECE37 3-3

32 First Integrator (INT) Shared Input/Reference Caps +Vref Vref 2 v 2 v C 2 3C V u V x U / 3 / 3 V z z 2 v 2 2 v +Vref Vref C 3C CM of V ref = CM of V u How do we determine C? ECE

33 kt/c Noise R C v n Fact: Regardless of the value of R, the meansquare value of the voltage on C is v n 2 kt C where k = J/K is Boltzmann s constant and T is the temperature in Kelvin The ms noise charge is q 2 n = C 2 v 2 n = ktc. = ECE

34 Derivation of kt/c Noise Equipartition of Energy physical principle: In a system at thermal equilibrium, the average energy associated with any degree of freedom is 2 kt. This applies to the kinetic energy of atoms (along each axis of motion), vibrational energy in molecules and to the potential energy in electrical components. Fact: The energy stored in a capacitor is --CV 2 2 So, according to equipartition, --CV, or 2 2 = --kt 2 V 2 kt = C ECE

35 Implications for an SC Integrator Each charge/discharge operation has a random component The amplifier plays a role during phase 2, but we ll assume that the noise in both phases is just kt/c. Trevor will revisit this assumption in Lecture 9. For a given cap, these random components are essentially uncorrelated, so the noise is white q C 2 2 q t = q +q 2 2 q 2 q 2 = q 2 2 = kt C q 2 t = q 2 + q 2 2 = 2kT C ECE

36 Integrator Implications (cont d) This noise charge is equivalent to a noise voltage with ms value v 2 n = 2kT C added to the input of the integrator: v n z z C C 2 This noise power is spread uniformly over all frequencies from 0 to f s 2 The power in the band [ 0, f B ] is v n2 OSR ECE

37 Differential Noise v n v n = v n + v n2 v n2 v n 2 = v 2 v n + 2 n2 Twice as many switched caps twice as much noise power The input-referred noise power in our differential integrator is v 2 n = 4kT C ECE

38 INT Absolute Capacitor Sizes For SNR = 00 3-dBFS input The signal power is v 2 ( V) s = = 0.25 V dbfs Therefore we want 2 = V 2 Since 2 = v n2 OSR v n, in-band C If we want 0 db more SNR, we need 0x caps ECE A v n, in-band 4kT = =.33 pf v n 2

39 Second Integrator (INT2) Separate Input and Feedback Caps 2 3C 9C X / 3 z z v 2 2 V x V ref 2 2 v v 2 v 3C C C V x2 ECE C CM of V x CM of V ref CM of op amp input / 9 V

40 INT2 Absolute Capacitor Sizes In-band noise of second integrator is greatly attenuated π = OSR INT pb edge: A ω B 3 = = Capacitor sizes not dictated by thermal noise Charge injection errors and desired ratio accuracy set absolute size A reasonable size for a small cap is currently ~0 ff. ω B OSR π INT2 noise attenuation: > OSR A ECE

41 Behavioral Schematic ECE37 3-4

42 Open-loop verification Loop filter Verification 2 Comparator Since MOD2 is a -bit system, all that can go wrong is the polarity and the timing. Usually the timing is checked by (), so this verification step is not needed. Closed-loop verification 3 Swing of internal states 4 Spectrum: SQNR, STF gain 5 Sensitivity, start-up, overload recovery, ECE

43 Loop-Filter Check Theory Open the feedback loop, set u = 0 and drive an impulse through the feedback path U =0 z z X X 2 z Q X 2 = z z Y z yn ( ) = { 00,,, } x 2 ( n) = { 2, 3, 4, } If x 2 is as predicted then the loop filter is correct At least for the feedback signal, which implies that the NTF will be as designed. ECE V

44 Loop Filter Check Practice * l(r) l(p) l(p2) l(v) 0 X x_matlab -00 xe X2 x2_matlab time, xe-6 Seconds *. In theory there is no difference between theory and practice. But in practice there is. ECE

45 Hey! You Cheated! An impulse is {,0,0, }, but a binary DAC can only output ±, i.e. it cannot produce a 0 Q: So how can we determine the impulse response of the loop filter through simulation? A: Do two simulations: one with v = {,,, } and one with v = {+,,, }. Then take the difference. According to superposition, the result is the response to v = {2,0,0, }, so divide by 2. To keep the integrator states from growing too quickly, you could also use v = {,,+,, } and then v = {+,,+,, }. ECE

46 Simulated State Swings.5 v(xp,xn) 3-dBFS ~300-Hz sine wave Swing < V p,diff v(x2p,x2n) Swing < V p,diff time (ms) ECE

47 0 db(spec) db(sqq) Unclear Spectrum freq, xe3 Hertz ECE

48 Professional Spectrum dbfs/nbw SQNR = 05 OSR = 500 Smoothed Spectrum 08-dBc 3 rd harmonic Theoretical PSD (k = ) k 0k 00k Frequency (Hz) NBW=46Hz SQNR dominated by 09-dBFS 3 rd harmonic ECE

49 Implementation Summary Choose a viable SC topology and manually verify timing 2 Do dynamic-range scaling You now have a set of capacitor ratios. Verify operation: loop filter, timing, swing, spectrum. 3 Determine absolute capacitor sizes Verify noise. 4 Determine op-amp specs and construct a transistor-level schematic Verify everything. 5 Layout, fab, debug, document, get customers, sell by the millions, go public, ECE

50 Differential vs. Single-Ended Differential is more complicated and has more caps and more noise single-ended is better? C/2 C ±V ±V ± V SNR C/2 ( 2V ) 2 2 CV V = = SNR 2 2 = = 4kT ( C 2) 4kT 2kT C CV kT Same capacitor area same SNR Differential is generally preferred due to rejection of even-order distortion and common-mode noise/ interference. ECE

51 Double-Sampled Input V u 2 2 C C 2 2 Doubles the effective input signal Allows C to be 4 the size for the same SNR Doubles the sampling rate of the signal, thereby easing AAF further ECE37 3-5

52 Shared vs. Separate Input Caps Separate caps More noise: C V input: v n 2 = 2kT C V V 2 C C 2 V 2 input: v n2 V 2 gain / V gain: 2 = 2kT C 2 C 2 C v n2 referred to V : v n2 C 2 C Total noise referred to V : ( 2kT C )( + C 2 C ) But using separate caps allows input CM to be different from reference CM, and so is often preferred in a general-purpose ADC ECE

53 Signal-Dependent Ref. Loading Another practical concern is the current draw from the reference V ref αsinωt V ref,actual ADC Output V in V ref ( εsinωt ) V in ( + εsinωt ) V ref If the reference current is signal-related, harmonic distortion can result ECE

54 Shared Caps and Ref. Loading +Vref Vref 2 v 2 v C 2 +V ref q C V u V u C 2 v 2 2 v +Vref Vref C q = C( V ref V u 2), v = + C( V ref + V u 2), v = ECE

55 Thus I = C --- V T ( ref v Vu 2) If u = Asinω u t, then v = u + error also contains a component at ω u and thus I contains a component at ω = 2ω u. Since ADC Output V in ( + εsinωt ), the signaldependent reference current in our circuit can produce 3 rd -harmonic distortion Also, the load presented to the driving circuit is dependent on v and this noisy load can cause trouble. With separate caps, the reference current is signal-independent Yet another reason for using separate caps. ECE

56 Unipolar Reference V ref v + 2 v C 2 q = v C V ref v DAC v (n ) v (n +) Be careful of the timing of v relative to the integration phase! ECE

57 Single-Ended Input Shared Caps V u V ref 2 v 2 v 2 v V ref C 2 2 C v 2 Full-scale range of V u is [0,V ref ]. 2 v (n ) v (n +) ECE

58 Homework #3 (Due ) Construct a differential switched-capacitor implementation of MOD2 using ideal elements (switches, capacitors, amplifiers, comparator) and verify it. Scale the circuit such that the full-scale differential input range is [,+] V and the op amp swing is 0.5 V p,diff at 6 dbfs. You may assume that 0.5-V and +0.5-V references are available and that the input is available in differential form. Choose capacitor values such that the SNR with a 6 dbfs input will be ~85 db when OSR = 28. You may assume that the only source of noise is kt/c noise. ECE

59 Homework Deliverables Schematic of MOD2 annotated with node voltages during reset (dc sim) 2 Open-loop impulse response plot (short transient sim) 3 Time-domain plots of input signal and integrator outputs for a 6-dBFS input (transient sim) 4 Spectrum of output data for a 6-dBFS input, with SNDR calculated 5 kt/c noise calculation (justify your choice of C) 6 Choose your own check and do it. ECE

60 What You Learned Today And what the homework should solidify MOD2 implementation 2 Switched-capacitor integrator Switched-C summer & DAC too 3 Dynamic-range scaling 4 kt/c noise 5 Verification strategy ECE