Four Voltage References, an ADC and MSP430

Transcription

1 Four Voltage References, an ADC and MSP430 Tadija Janjic HPL Tucson Michael Ashton DAP

2 Motivation u Total Solution Concept u Application section of datasheets u New REF products from TI u Greed Product Recognition Increased Revenue 2

3 Experiment u Verify setup/measurements u Evaluate TI REFs with ADS1256 u Compare different TI REF results u Suggest the optimal circuitry 3

4 Basic Setup Vss R2 R2 1k To ADS Vref R1 R1 1k -!OPAMP Vref C1 1u C1 C2 1u C2 ADS1256, PGA=1, Vref=2.5V 4

5 Board 5

6 Board (side view) 6

7 Considerations u Low Noise u Long term stability Time Temperature 7

8 Experiment Design R1 C1 OPA R2 C2 RMS noise free bits u u Additional considerations: Vin amplitude, f s (data output rate) 8

9 Confirm the Setup REF R1 C1 OPA R2 C2 RMSnfb k 47u u 23.8 VIn=0V, shorted inputs, 9

10 Results REF R1 C1 OPA R2 C2 RMSnfb OPA u k 220u same same same k 47u same same same same same same same same same same same same same * same same same same same same same OPA227 same same 22.4 Vin=2.5V, data output rate = 60Hz, * OPA in a gain of 2 10

11 Conclusions u On ADS1256 one needs external buffer Input impedance 18k u Noise-wise OPA227 and OPA335 equal However, we tried at T=25 C u REF1004 and REF1112 similar results u REF3xxx family good for lower precision u RC (settling time vs. noise) trade off 11

12 MSP430 u Has 12 bit ADC (ADC12) u Has Vref (2.5V or 1.5V) 800uA max 100ppm/ C max 4% initial accuracy TI REFs: 8uA -110 ua max current ppm/ C 2.048/2.5/3.0V/3.3V 0.2% 12

13 Results REF R1 C1 Noise RMS bits Internal (2.5V) ~ V u ~ k 47u ~ same same ~ same same ~ same ~ same same ~ same same

14 Conclusions Part II u External REFs improve performance Lower noise Lower supply current u REF1112 can not be used with MSP430 VeRef is 1.4V min!!!!! 14

15 Summary u Built tools for evaluations u Got preliminary results u Will work on other ADCs and MSP430 SARs, Delta-Sigma u Will improve datasheets u Support customers with optimal solution Thank You 15

16 Amplifier to A/D Interface Study Or that short task that will not go away Generated by Foxit PDF Creator Foxit Software Bill Klein Senior Applications Engineer Miro Oljaca Strategic Marketing: Motor Control With major contributions from: Tom Hendrick, Tim Green, Rick Downs, Rod Burt, Bob Benjamin, Bernd Rundel, Bruce Trump, Dennis Goeke, Pat Highton 16

17 The Interface Circuit R C sw samp R sw C SH (20pF to 50pF) V int (V cc, 0.5V cc, or GND) sw conv Op Amp Filter A/D CMV Range, V OS vs CMV Charge Bucket Acquisition Time RR Out-Swing to the rail Filtering, Input Circuit Parameters Slew Rate, Signal BW, C load Isolation, Initial Voltage on C SH Load Transient, Settling Time, Output Impedance, 17

18 LSB Size usignal range: +/-10V is a 20V range 12 bits: 20V/4,096 = 4.88mV per LSB 16 bits: 20V/65,536 = 305µV per LSB +5V range 12 bits: 5V/4,096 = 1.22mV per LSB 16 bits: 5V/65,536 = 76.2µV per LSB 24 bits: 5V/16,777,216 = 298nV per LSB +3.3V range 12 bits: 3.3V/4,096 = 806µV per LSB 16 bits: 3.3V/65,536 = 50.4µV per LSB 24 bits: 3.3V/16,777,216 = 196nV per LSB 18

19 Op Amp Input Concerns See Appendix R C sw samp R sw C SH (20pF to 50pF) V int (V cc, 0.5V cc, or GND) sw conv Rail-to-Rail Input 19

20 Output Stage Concerns See Appendix R C sw samp R sw C SH (20pF to 50pF) V int (V cc, 0.5V cc, or GND) sw conv Rail-to-Rail Output 20

21 How Fast does that Op Amp Settle R C sw samp R sw C SH (20pF to 50pF) V int (V cc, 0.5V cc, or GND) sw conv 21

22 What Settling Time? uthink of a linear voltage regulator, there are TWO Settling Times. Line Transient Load Transient usame applies here. udata sheets report settling time to 0.01% at best. 22

23 The Test Circuit C fb REF V-1 +15V-1 OPA227-15V V 2.0K 10K +5V DUT R fil C fil Ref ADS K 10K 2.5V ADS CMD Acquire Convert 30usec T Conv Acq Conv Increment in 20nsec steps 4.0V DUT Out 0.5V 23

24 OPA Bits Series1 Series2 Series3 Series Time (nsec) 24

25 OPA Series1 Series

26 OPA

27 Line Transient Becomes uresponse to change in input signal uincludes Slew Rate. uop Amp data sheets MAY address Settling Time to 0.01% ubut we need % for a 16 bit system 27

28 Required Settling Time Number of bits 0.5LSB % % % % % % % % See appendix for calculations 28

29 Load Transient is UNKNOWN uwe know the load is the input capacitance of the A/D uwe do NOT know the starting voltage. Possible voltages: GND, Mid-Rail, Random Not given in data sheet uthe Op Amp data sheet does NOT even mention this settling time. 29

30 SAR A/D < 500kHz u 70% Applications Slow Moving Real World Process Signals Fast Acquisition & Conversion Allows More System Time For Processing, Computation, Decision Making Multiplexed, Scanning Systems for Slow Moving Signals u 30% Applications AC Fast Moving Dynamic Signals Real Time Processing of Input Signals 30

31 Look at the Charge Transients 31

32 Capacitor Type is Critical R C sw samp R sw C SH (20pF to 50pF) V int (V cc, 0.5V cc, or GND) sw conv 32

33 THD+N vs. Frequency for Various Capacitor types d B k 2k 5k 10k 20k 50k 100k 200k Hz Sweep Trace Color Line Style Thick Data Axis Comment 1 1 Yellow Solid 1 Anlr.THD+N Ratio Left C = Red Solid 1 Anlr.THD+N Ratio Left C1 3 1 Blue Solid 1 Anlr.THD+N Ratio Left C2 4 1 Cyan Solid 1 Anlr.THD+N Ratio Left C3 5 1 Green Solid 1 Anlr.THD+N Ratio Left C4 R = 100 ohm, C = 3.3 nf, Vp-p = 5V f(-3db) = 482 khz 33

34 THD+N vs. Voltage for Various Capacitor Types d B Vrms Sweep Trace Color Line Style Thick Data Axis Comment 1 1 Yellow Solid 1 Anlr.THD+N Ratio Left C = Red Solid 1 Anlr.THD+N Ratio Left C1 3 1 Blue Solid 1 Anlr.THD+N Ratio Left C2 4 1 Cyan Solid 1 Anlr.THD+N Ratio Left C3 5 1 Green Solid 1 Anlr.THD+N Ratio Left C4 R = 100 ohm, C = 3.3 nf, f = 10 khz, f(-3db) = 482 khz 34

35 Conclusions on C Type ubest performance: Sliver Mica or COG(NPO) uavoid all other uothers may cost less and be smaller but can distort signal 35

36 Selecting the Fly-wheel Values R C sw samp R sw C SH (20pF to 50pF) V int (V cc, 0.5V cc, or GND) sw conv 36

37 Fly Wheel Component Selection u Pick C =20*C SH (See Appendix for proof) u R Calculation t _settle = t SAMPL = 12 τ FLT Theoretical Minimum Practical results Use t =18τ FLT Margin for: Op Amp Output Load Transient Op Amp Output Small Signal Settling Time R = t SAMPL /18 C 37

38 ADC Sampling Considerations Voltage on the sampling capacitor during sampling period V C ( t) = V0 + ( E V0 ) (1 e t τ ) 1) E V V t C ( t ) AQ 1 2 LSB 1 ) E (1 2 C ( AQ 17 t AQ τ E V ln( E ) ) 38

39 ADC Sampling Considerations Suggested input sampling switch transient-immunity RC filter R SW R SW V C C C S V 0 τ E ln( t AQ V E ) 39

40 Required Settling Time Number of bits 0.5LSB Time Constants % % % % % % % % 18 See appendix for calculations 40

41 Establish Op Amp Specs Determine Op Amp specs needed based on system values set in design. Op Amp specs to be determined: uugbw uslew Rate ui out 41

42 Impact on UGBW u Modified A ol due to R FLT & C FLT f PX = 1/[2 Π(R O + R FLT )C FLT ] f ZX = 1/[2 Π R FLT C FLT ] u Stability Check At f cl Rate-of-closure is 20dB/decade f ZX cancels f PX before f cl f PX and f ZX are < decade apart Phase of pole will be cancelled by phase of zero This implies: R FLT < 9 R O u Impact on UGBW UGBW mod = UGBW orig -(f ZX - f PX ) 42

43 Impact on UGBW-cont 43

44 Op Amp Specs to Check uugbw mod >2* 1/[2 Π R FLT C FLT ] uop Amp Transient Output Drive to R FLT & C FLT I Opk max = (5% V REF )/(R FLT ) 44

45 Interface Design Check List uop Amp Common Mode Voltage uop Amp Output Swing to Rail uop Amp Settling Time ufilter Capacitor Type ufilter Component Values uop Amp Specifications 45

46 Appendix Calculation Details 1.C as a Function of C sh 2.Open Loop Output Resistance vs. Closed Loop Output Resistance 3.Modified A ol Calculations 4.Time to Charge Capacitor 46

47 Op Amp Input Concerns R C sw samp R sw C SH (20pF to 50pF) V int (V cc, 0.5V cc, or GND) sw conv Rail-to-Rail Input 47

48 Input Stage-Parallel P-ch & N-ch +V SUPPLY V IN - Q 1 Q 2 V IN + Q 3 Q 4 -V SUPPLY 48

49 Looking at Input Stage Performance 1.0kΩ 1.0kΩ kΩ 100kΩ Gain=100 49

50 Single Supply RRI Plot-V OS vs CMV (Most RRI Op Amps Except OPA363/OPA364) OPA2340 (Dual: V OUT1 & V OUT2 from different halves) CMV V OUT1 V OUT2 50

51 Performance Requirements The simple buffer stage. Most accurate unity gain. V IN - + V+ V OUT Bits (mv) (db)

52 OPA350 Data Sheet THD+N 52

53 Possible Input Schemes - V+ V OUT V B - V+ V OUT V IN + (A) Good V IN + (B) Better V IN - V+ V OUT V B + (C) Best 53

54 OPA350 THD+N vs Frequency d B k 2k 5k 10k 20k 50k 100k 200k Hz Sweep Trace Color Line Style Thick Data Axis Comment 1 1 Yellow Solid 1 Anlr.THD+N Ratio Left OPA350 High CMRR G= Red Solid 1 Anlr.THD+N Ratio Left OPA350 High CMRR G= Blue Solid 1 Anlr.THD+N Ratio Left OPA350 Low CMRR G= Cyan Solid 1 Anlr.THD+N Ratio Left OPA350 Low CMRR G=-1 OPA 350, R = 0 ohm, C = 0 nf, Vp-p = 4 V, G = +1or -1 54

55 OPA350 with RC, THD+N vs Frequency d B k 2k 5k 10k 20k 50k 100k 200k Hz Sweep Trace Color Line Style Thick Data Axis Comment 1 1 Yellow Solid 1 Anlr.THD+N Ratio Left OPA350 Low CMRR G=+1 C1 2 1 Red Solid 1 Anlr.THD+N Ratio Left OPA350 Low CMRR G=-1 C4 OPA 350, R = 100 ohm, C = 3.3 nf, Vp-p = 4 V, f(-3db) = 482 khz, G = +1or -1 55

56 OPA350 THD+N vs Input Voltage d B Vpp Sweep Trace Color Line Style Thick Data Axis Comment 1 1 Yellow Solid 1 Anlr.THD+N Ratio Left OPA350 Low CMRR 1kHz 2 1 Red Solid 1 Anlr.THD+N Ratio Left OPA350 Low CMRR 10kHz 3 1 Cyan Solid 1 Anlr.THD+N Ratio Left OPA350 Low CMRR 50kHz 4 1 Green Solid 1 Anlr.THD+N Ratio Left OPA350 Low CMRR 100kHz OPA 350, R = 0 ohm, C = 0 nf, G = -1 56

57 Output Stage Concerns R C sw samp R sw C SH (20pF to 50pF) V int (V cc, 0.5V cc, or GND) sw conv Rail-to-Rail Output 57

58 OPA KHz 10KHz -50 THD+N V(out) 58

59 OPA KHz 10KHz -50 THD+N V(out) 59

60 Solution Circuit - + +In ADS8361 usince Op Amp can only swing 4.8Vp-p uset ADS FSR to 4.8V by reducing Ref in to 2.4V. 2.5V -In Ref Out Ref In 2.4V 60

61 Filter Design Example u R SW = 100Ω (Not needed for Buffer & Filter Calculations) u C SH = 50pF [for ADS8361] u Worst case ΔV across C SH is V REF V REF = +5V u t SAMPL = 1.88μs [for ADS8361] 61

62 Filter Design Example(cont) u Charge Transfer Equation: Q = CV u Charge required to charge C SH to V REF Q SH = C SH V REF Q SH = 50pF 5V = 250pC u IDEAL C FLT Charge Bucket to fill C SH with only a 76μV (1/2LSB) droop on C FLT Q FLT =Q SH Q FLT = C FLT (38μV) 250pC = C FLT (38μV) C FLT = 6.6μF u IDEAL C FLT = 6.6μF Not a good, small, cheap high frequency ceramic capacitor Not practical for Op Amp to drive directly (stability, transient current) Isolation resistor likely not large enough to help isolate Cload and still meet necessary filter time constant 62

63 Filter Design Example(cont) u Partition the Charge Bucket 95% from C FLT 5% from Op Amp u C FLT value required to provide Q SH with <5% droop on C FLT Q FLT = Q SH Q FLT = C FLT (0.05V REF ) 250pC = C FLT (0.05 5V) C FLT = 1nF u During t SAMPL the Op Amp must provide 5% V REF to C FLT Ensure C FLT is at least 10X > C SH This implies dominant load for Op Amp Buffer is C FLT 1nF = 20 X 50pF C FLT = 20X C SH 63

64 Op Amp Model for Derivation of R OUT 64

65 Derivation of R OUT (Closed Loop Output Resistance) β = V FB /V OUT = [V OUT (R I / {R F + R I })]/V OUT = R I / (R F + R I ) R OUT = V OUT /I OUT V O = -V E Aol V E = V OUT [R I /(R F + R I )] V OUT = V O + I OUT R O V OUT = -V E Aol + I OUT R O V OUT = -V OUT [R I /(R F + R I )] Aol+ I OUT R O V OUT + V OUT [R I /(R F + R I )] Aol = I OUT R O V OUT = I OUT R O / {1+[R I Aol/(R F +R I )]} R OUT = V OUT /I OUT = I OUT R O / {1+[R I A OL /(R F +R I )]} R OUT = R O / (1+Aolβ)

66 OPA353 Specifications R O = 40Ω R OUT (@1MHz, G=10) = 10Ω = 29.54dB = x30 66

67 OPA353 R OUT Calculation R O = 40Ω R OUT (@1MHz, G=10) = 10Ω = 29.54dB = x30 67

68 R OUT vs R O u R O does not change when feedback is used to close the loop u Closed loop feedback forces V O to increase/decrease u The increase/decrease in V O appears at V OUT as a reduction in R O u R OUT is the net effect of R O and closed loop feedback controlling V O 68

69 Op Amp Model for AC Stability Analysis R O is constant over the Op Amp s bandwidth R O is defined as the Op Amp s Open Loop Output Resistance R O is measured at I OUT = 0 Amps, f = 1MHz R O is included in β calculation 69

70 Aol Modified by Filter Original Aol f P f Z E E E E E+07 70

71 Modified Aol-The Math V OUT = V R O O R + R 1 + sc 1 + sc V OUT V O = K = 1 R + sc 1 RO + R + sc V OUT V O = K = sc sc + 1 ( R + R ) + 1 O R V OUT V O = K = C ( R + R ) C O s + C R 1 R s + C 1 R 71

72 72 Modified Aol-The Math cont. ( ) ( ) = = O f f O O OUT R R C R C R C s R R C R C R C s K V V 1 1 ( ) ( ) = = O O O OUT R R R R C s R R R R C s K V V 1 1 ( ) ( ) = = O O O OUT R R C s R C s R R R K V V 1 1 ( ) z O p R C f R R C f Π = + Π = 2 1 ; 2 1 Generated by Foxit PDF Creator Foxit Software

73 Voltage on the sampling capacitor during sampling period VC ( t) = V0 + ( E V0 ) (1 e 1 E VC ( taq) LSB 2 V 1 ) E (1 2 C ( t AQ 17 t AQ τ E V ln( E ) ) t τ ) 73