Oversampling Converters

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1 Oversampling Converters David Johns and Ken Martin slide 1 of 56

2 Motivation Popular approach for medium-to-low speed A/D and D/A applications requiring high resolution Easier Analog reduced matching tolerances relaxed anti-aliasing specs relaxed smoothing filters More Digital Signal Processing Needs to perform strict anti-aliasing or smoothing filtering Also removes shaped quantization noise and decimation (or interpolation) slide 2 of 56

3 Quantization Noise en ( ) xn ( ) yn ( ) xn ( ) yn ( ) en ( ) = yn ( ) xn ( ) Quantizer Model Above model is exact approx made when assumptions made about en () Often assume en () is white, uniformily distributed number between ± 2 is difference between two quantization levels slide 3 of 56

4 Quantization Noise T time White noise assumption reasonable when: fine quantization levels signal crosses through many levels between samples sampling rate not synchronized to signal frequency Sample lands somewhere in quantization interval leading to random error of ± 2 slide 4 of 56

5 Quantization Noise Quantization noise power shown to be 2 12 and is independent oampling frequency If white, then spectral density of noise, S e ( f ), is constant. S e () f Height k x = f slide 5 of 56

6 Oversampling Advantage Oversampling occurs when signal of interest is bandlimited to f 0 but we sample higher than 2 f 0 Define oversampling-rate OSR = ( 2 f 0 ) After quantizing input signal, pass it through a brickwall digital filter with passband up to f 0 (1) y 1 ( n) un ( ) Hf () y 2 ( n) N-bit quantizer Hf () 1 0f f f 0 slide 6 of 56

7 Oversampling Advantage Output quantization noise after filtering is: P e = S e( f ) H( f) df = k x df = 2 Doubling OSR reduces quantation noise power by 3dB (i.e. 0.5 bits/octave) Assuming peak input is a sinusoidal wave with a peak value of 2 N ( 2) leading to P s = (( 2 N ) ( 2 2) ) 2 Can also find peak SNR as: f 0 f OSR (2) P s SNR max = 10 log = 10 P e 3 log --2 2N + 10 log( OSR) 2 (3) slide 7 of 56

8 Example Oversampling Advantage A dc signal with 1V is combined with a noise signal uniformily distributed between ± 3 giving 0 db SNR. {0.94, 0.52, 0.73, 2.15, 1.91, 1.33, 0.31, 2.33}. Average of 8 samples results in Signal adds linearly while noise values add in a square-root fashion noise filtered out. Example 1-bit A/D gives 6dB SNR. To obtain 96dB SNR requires 30 octaves of oversampling ( (96-6)/3 db/octave ) If f 0 = 25 khz, = 2 30 f 0 = 54, 000 GHz! slide 8 of 56

9 Advantage of 1-bit D/A Converters Oversampling improves SNR but not linearity To acheive 16-bit linear converter using a 12-bit converter, 12-bit converter must be linear to 16 bits i.e. integral nonlinearity better than LSB A 1-bit D/A is inherently linear 1-bit D/A has only 2 output points 2 points always lie on a straight line Can acheive better than 20 bits linearity without trimming (will likely have gain and offset error) Second-order effects (such as D/A memory or signaldependent reference voltages) will limit linearity. slide 9 of 56

10 Oversampling with Noise Shaping Place the quantizer in a feedback loop xn ( ) un ( ) yn ( ) Hz () xn ( ) un ( ) yn ( ) Hz () Quantizer Delta-Sigma Modulator en ( ) Linear model slide 10 of 56

11 Oversampling with Noise Shaping Shapes quantization noise away from signal band of interest Signal and Noise Transfer-Functions Yz () S TF () z Uz Hz () = () 1 + Hz () Yz () N TF () z = Ez () 1 + Hz () Yz () = S TF ()Uz z + N TF ()Ez z Choose Hz () to be large over 0 to f 0 Resulting quantization noise near 0 where Hz () large Signal transfer-function near 1 where Hz () large (4) (5) (6) slide 11 of 56

12 Oversampling with Noise Shaping Input signal is limited to range of quantizer output when Hz () large For 1-bit quantizers, input often limited to 1/4 quantizer outputs Out-of-band signals can be larger when Hz () small Stability of modulator can be an issue (particularily for higher-orders of Hz () Stability defined as when input to quantizer becomes so large that quantization error greater than ± 2 said to overload the quantizer slide 12 of 56

13 First-Order Noise Shaping Choose Hz () to be a discrete-time integrator Hz () = z 1 (7) un ( ) z 1 xn ( ) Quantizer yn ( ) Itable, average input of integrator must be zero Average value of un () must equal average of yn () slide 13 of 56

14 Example The output sequence and state values when a dc input, un (), of 1 3is applied to a 1 st order modulator with a two-level quantizer of ± 1.0. Initial state for xn ( ) is 0.1. n x(n) x(n + 1) y(n) e(n) Average of yn () is 1 3as expected Periodic quantization noise in this case slide 14 of 56

15 Transfer-Functions Signal and Noise Transfer-Functions S TF () z N TF () z Yz () 1 ( z 1) = = Uz () = + 1 ( z 1) z 1 Yz () 1 = = Ez () = ( 1+ 1 ( z 1) 1 z 1 ) Noise transfer-function is a discrete-time differentiator (i.e. a highpass filter) e jπf e jπf N TF ( f ) 1 e 2πf j = = j e jπf 2 j πf sin j e jπf = (8) (9) (10) slide 15 of 56

16 Signal to Noise Ratio Magnitude of noise transfer-function N TF ( f ) = 2 sin πf (11) Quantization noise power P e f 0 2 = S e( f ) N TF ( f ) 2 df = f 0 f 0 f sin πf df (12) Assuming f 0 << (i.e., OSR >> 1) 2 P e π f 0 3 = 2 π OSR (13) slide 16 of 56

17 Max SNR Assuming peak input is a sinusoidal wave with a peak value of 2 N ( 2) leading to P s Can find peak SNR as: = (( 2 N ) ( 2 2) ) 2 SNR max = 10 = 10 or, equivalently, P s log P e 3 log --2 2N + 10 log ( OSR) 3 SNR max = 6.02N log( OSR) Doubling OSR gives an SNR improvement 9dBor, equivalently, a benefit of 1.5 bits/octave π 2 (14) (15) slide 17 of 56

18 SC Implementation Quantizer un ( ) yn ( ) z 1 Hz () Analog 1-bit D/A Digital C V in φ 1 C φ 2 Comparator φ 2 φ 1 V out V ref 2 φ 2, ( φ 1 ) φ 1, ( φ 2 ) C Latch on φ 2 falling φ 1, φ 2 V out high ( φ 1 ),( φ 2 ) V out low slide 18 of 56

19 Second-Order Noise Shaping un ( ) z 1 yn ( ) z 1 Quantizer S TF ( f ) = z 1 N TF ( f ) = ( 1 z 1 ) 2 SNR max = 6.02N log( OSR) Doubling OSR improves SNR by 15 db (i.e., a benefit of 2.5 bits/octave) (16) (17) (18) slide 19 of 56

20 Noise Transfer-Function Curves Second-order N TF () f First-order No noise shaping 0 f f 0 s f Out-of-band noise increases for high-order modulators Out-of-band noise peak controlled by poles of noise transfer-function Can also spread zeros over band-of-interest slide 20 of 56

21 Example 90 db SNR improvement from A/D with Oversampling with no noise shaping From before, straight oversampling requires a sampling rate of 54,000 GHz. First-Order Noise Shaping Lose 5 db (see (15)), require 95 db divided by 9 db/ octave, or octaves = f 0 75 MHz Second-Order Noise Shaping Lose 13 db, required 103 db divided by 15 db/ octave, = 5.8 MHz (does not account for reduced input range needed for stability). f 0 = 25 khz slide 21 of 56

22 Quantization Noise Power of 1-bit Modulators If output of 1-bit mod is ±1, total power of output signal, yn (), is normalized power of 1 watt. Signal level often limited to well below ±1 level in higher-order modulators to maintain stability For example, if maximum peak level is ±0.25, max signal power is 62.5 mw. Max signal is approx 12 db below quantization noise (but most noise in different frequency region) Quantization filter must have dynamic range capable of handling full power of yn () at input. Easy for A/D digital filter More difficult for D/A analog filter slide 22 of 56

23 Write Hz () as Zeros of NTF are poles of H(z) xn ( ) un ( ) yn ( ) Hz () NTF is given by: NTF() z Hz () = Quantizer Nz () Dz () 1 = = 1 + Hz () Dz () Dz () + Nz () If poles of Hz () are well-defined then so are zeros of NTF (19) (20) slide 23 of 56

24 Error-Feedback Structure Alternate structure to interpolative un ( ) xn ( ) yn ( ) Gz () 1 en ( ) Signal transfer-function equals unity while noise transfer-function equals Gz () First element of Gz () equals 1 for no delay free loops 1 First-order system Gz () 1= z More sensitive to coefficient mismatches slide 24 of 56

25 Architecture of Delta-Sigma A/D Converters x in () t x c () t x sh () t x x lp ( n) dsm ( n) x s ( n) Antialiasing filter Sampleandhold Σ Mod Digital low-pass filter OSR 2f 0 Analog Digital Decimation filter x c () t x sh () t X c () f t f 0 X sh () f f f 0 f Time Frequency slide 25 of 56

26 Architecture of Delta-Sigma A/D Converters x ( n) = ± dsm X ( ω) dsm n 2πf 0 2π ω x lp ( n) X lp ( ω) 123 n 2πf 0 2π ω x s ( n) X s ( ω) n π 2π 4π 6π 8π 10π 12π ω Time Frequency slide 26 of 56

27 Architecture of Delta-Sigma A/D Converters Relaxes analog anti-aliasing filter Strict anti-aliasing done in digital domain Must also remove quantization noise before downsampling (or aliasing occurs) Commonly done with a multi-stage system Linearity of D/A in modulator important results in overall nonlinearity Linearity of A/D in modulator unimportant (effects reduced by high gain in feedback of modulator) slide 27 of 56

28 Architecture of Delta-Sigma D/A Converters x s ( n) x s2 ( n) x lp ( n) x dsm ( n) x da () t x c () t OSR Interpolation (low-pass) filter Σ Mod 2f 0 1-bit D/A Analog low-pass filter OSR f 0 x s ( n) x s2 ( n) Digital X s ( ω) Analog 123 ( 1) ( 2) ( 3) n π 2π 4π 6π 8π 10π 12π X s2 ( ω) ω ( 2πf 0 ) 2π ω Time Frequency slide 28 of 56

29 Architecture of Delta-Sigma D/A Converters x lp ( n) 123 x dsm ( n) x da () t n X lp ( ω) ( 2πf 0 ) X dsm ( ω) 2π ω n, t ( 2πf 0 ) 2π ω X da () f x c () t f 0 f t X c () f Time f 0 Frequency f slide 29 of 56

30 Architecture of Delta-Sigma D/A Converters Relaxes analog smoothing filter (many multibit D/A converters are oversampled without noise shaping) Smoothing filter of first few images done in digital (then often below quantization noise) Order of lowpass filter should be at least one order higher than that of modulator Results in noise dropping off (rather than flat) Analog filter must attenuate quantization noise and should not modulate noise back to low freq strong motivation to use multibit quantizers slide 30 of 56

31 Lth-order Σ modulator Multi-Stage Digital Decimation Rate = Rate = 8f 0 Rate = 2f 0 T sinc () z T IIR () z Sinc L+ 1 IIR filter FIR filter Lth-order Σ modulator Rate = Rate = 8f 0 Rate = 4f Rate = 2f 0 0 T sinc () z H 1 () z H 2 () z H 3 () z Rate = 2f 0 Sinc L+ 1 Halfband FIR filters FIR filter Sinc compensation FIR filter Sinc filter removes much of quantization noise Following filter(s) anti-aliasing filter and noise slide 31 of 56

32 Sinc Filter sinc L+1 is a cascade of L+1 averaging filters Averaging filter T avg () z Yz () = = Uz () M z i M i = 0 M is integer ratio of ( 8 f 0 ) It is a linear-phase filter (symmetric coefficients) If M is power of 2, easy division (shift left) Can not do all decimation filtering here since not sharp enough cutoff (21) slide 32 of 56

33 Sinc Filter Consider x in () n = { 11,, 1, 1, 1, 1,... } applied to M = 4 averaging filters in cascade x 1 () n x 2 () n x 3 () n x T avg () z T avg () z T avg () z in () n sinc 3 filter x 1 ( n) = { 0.5, 0.5, 0.0, 0.5, 0.5, 0.0,... } x 2 ( n) = { 0.38, 0.38, 0.25, 0.38, 0.38, 0.25,...} x 3 ( n) = { 0.34, 0.34, 0.31, 0.34, 0.34, 0.31,...} Converging to sequence of all 1/3 as expected slide 33 of 56

34 Sinc Filter Response Can rewrite averaging filter in recursive form as T avg () z Yz () = = Uz () z M M 1 z 1 and a cascade of L + 1 averaging filters results in T sinc () z = z M L z 1 M L 1 Use L + 1 cascade to roll off quantization noise faster than it rises in L th order modulator (22) (23) slide 34 of 56

35 Let z Sinc Filter Frequency Response = e jω T avg e jω ( ) = sinc ωm sinc ω (24) where sinc() x sin( x) x 1 T avg e jω ( ) 0 π 2π ω slide 35 of 56

36 In T sinc () z Sinc Implementation = L z 1 ( 1 z M ) L M L z 1 z 1 z M z M ---- M (Integrators) (Differentiators) (25) Out In z 1 z 1 M ---- z 1 z 1 Out (Operate at high clock rate) M M (Operate at low clock rate) If 2 s complement arithmetic used, wrap-around okay since followed by differentiators slide 36 of 56

37 Higher-Order Modulators An L th order modulator improves SNR by 6L+3 db/octave Interpolative Architecture un ( ) c c 1 c 4 2 f c 1 3 f 2 c 5 a 1 a 2 a 3 a 4 a 5 Can spread zeros over freq of interest using resonators with f 1 and f 2 Need to worry about stability (more later) slide 37 of 56

38 MASH Architecture Multi-stAge noise SHaping - MASH Use multiple lower order modulators and combine outputs to cancel noise of first stages un ( ) z 1 1 e 1 z 1 un ( ) + ( 1 z 1 )e 1 ( n) 1-bit D/A z 1 e 1 ( n) 1-bit D/A z 1 2 e 2 z 1 yn ( ) Analog Digital z 1 e 1 ( n) + ( 1 z 1 )e 2 ( n) slide 38 of 56

39 Output found to be: Multibit Output MASH Architecture Yz () = z 2 Uz () ( 1 z 1 ) 2 E 2 () z Output is a 4-level signal though only single-bit D/A s if D/A application, then linear 4-level D/A needed if A/D, slightly more complex decimation A/D Application Mismatch between analog and digital can cause firstorder noise,, to leak through to output e 1 Choose first stage as higher-order (say 2 nd order) (26) slide 39 of 56

40 Bandpass Oversampling Converters Choose Hz () to have high gain near freq f c NTF shapes quantization noise to be small near f c OSR is ratio oampling-rate to twice bandwidth not related to center frequency 4 = 1 MHz z-plane zero 4 = 1 MHz z-plane zero 2f o dc f dc 2 = 4 MHz 2 = 4MHz f 0 Lowpass = 10 khz f = 10 khz f OSR = = 200 s 2f 0 Bandpass OSR = = 200 2f slide 40 of 56

41 Bandpass Oversampling Converters Hz () un ( ) z 1 yn ( ) z 1 Quantizer Above Hz () has poles at ± j (which are zeros of NTF) Hz () is a resonator with infinite gain at 4 Hz () = z ( z 2 + 1) Note one zero at +j and one zero at -j similar to lowpass first-order modulator only 9 db/octave For 15 db/octave, need 4 th order BP modulator slide 41 of 56

42 Modulator Stability Since feedback involved, stability is an issue Considered stable if quantizer input does not overload quantizer Non-trivial to analyze due to quantizer There are rigorous tests to guarantee stability but they are too conservative For a 1-bit quantizer, heuristic test is: N TF ( e jω ) 1.5 for 0 ω π Peak of NTF should be less than 1.5 Can be made more stable by placing poles of NTF closer to its zeros Dynamic range suffers since less noise power pushed out-of-band (27) slide 42 of 56

43 Modulator Stability NTF less stable more stable same area under two curves 2πf 0 2π ω Stability Detection Might look at input to quantizer Might look for long strings of 1s or 0s at comp output When instability detected... reset integrators Damp some integrators to force more stable slide 43 of 56

44 Linearity of Two-Level Converters For high-linearity, levels should NOT be a function of input signal power supply variation might cause symptom Also need to be memoryless switched-capacitor circuits are inherently memoryless if enough settling-time allowed Above linearity issues also applicable to multi-level A nonreturn-to-zero is NOT memoryless Return-to-zero is memoryless if enough settling time Important for continuous-time D/A slide 44 of 56

45 V 2 Linearity of Two-Level Converters Ideal Typical V 1 Binary Area for symbol A + δ A A + δ A Nonreturn-to-zero (NRZ) A + δ A + δ A + δ V 2 Ideal Typical V 1 Binary Area for symbol A 1 A 1 A 0 A 0 A 1 A 0 A 1 Return-to-zero (RTZ) slide 45 of 56

46 Idle Tones 1/3 into 1 st order modulator results in output yn () = { 11,, 1, 1, 1, 1, 1, 1,... } Fortunately, tone is out-of-band at 3 ( ) = 3 8 into modulator has tone at 16 Similar examples can cause tones in band-of-interest and are not filtered out say 256 Also true for higher-order modulators Human hearing can detect tones below noise floor Tones might not lie at single frequency but be short term periodic patterns. could be a tone varying between 900 and 1100 Hz varying in a random-like pattern (28) slide 46 of 56

47 Dithering Dither signal un ( ) Hz () yn ( ) Quantizer Add pseudo-random signal into modulator to break up idle tones (not just mask them) If added before quantizer, it is noise shaped and large dither can be added. A/D: few bit D/A converter needed D/A: a few bit adder needed Might affect modulator stability slide 47 of 56

48 Opamp Gain Finite opamp gain, A, moves pole at z = 1 left by 1 A z-plane zero NTF 1 A 2πf 0 A low opamp gain 2π ω Flattens out noise at low frequency only 3 db/octave for high OSR Typically, require A > OSR π (29) slide 48 of 56

49 Multi-bit Oversampled Converters A multi-bit DAC has many advantages more stable - higher peak NTF higher input range less quantization noise introduced less idle tones (perhaps no dithering needed) Need highly linear multi-bit D/A converters Example A 4-bit DAC has 18 db less quantization noise, up to 12 db higher input range perhaps 30 db improved SNR over 1-bit Large Advantage in DAC Application Less quantization noise easier analog lowpass filter slide 49 of 56

50 Multi-bit Oversampled Converters C C b 1 b 2 b 3 Thermometer-type decoder Eight-line randomizer C C C C C Analog output C Randomize thermometer code Can also shape nonlinearities slide 50 of 56

51 Third-Order A/D Design Example All NTF zeros at z = 1 NTF( z) = ( z 1) Dz ( ) Find Dz () such that NTF( e jω ) < 1.4 Use Matlab to find a Butterworth highpass filter with peak gain near 1.4 If passband edge at 20 then peak gain = 1.37 (30) NTF() z = ( z 1) z z z (31) slide 51 of 56

52 Third-Order A/D Design Example ω = π 2 1 j z-plane Three zeros at ω = 0 ω = π j 1 Butterworth poles Find Hz () as H( z) = 1 NTF( z) NTF( z) (32) H( z) = z z ( z 1) 3 (33) slide 52 of 56

53 Third-Order A/D Design Example Choosing a cascade of integrator structure un ( ) α 1 V α 2 V α 3 z 1 V z 1 z 1 Quantizer yn ( ) β 1 β 2 β 3 1-bit D/A Analog Digital α i coefficients included for dynamic-range scaling initially α 2 = α 3 = 1 last term, α 1, initially set to β 1 so input is stable for a reasonable input range Initial β i found by deriving transfer function from 1-bit D/A output to V 3 and equating to Hz () slide 53 of 56

54 Third-Order A/D Design Example z 2 ( β H( z) 1 + β 2 + β 3 ) z( β 2 + 2β 3 ) + β = ( z 1) 3 Equating (33) and (34) results in α 1 = , α 2 = 1.0, α 3 = 1.0 β 1 = , β 2 = , β 3 = (34) (35) slide 54 of 56

55 Third-Order A/D Design Example Dynamic Range Scaling Apply sinusoidal input signal with peak value of 0.7 and frequency π 256 rad/sample Simulation shows max values at nodes V 1, V 2, V 3 of , , and Can scale node V 1 by k 1 by multiplying α 1 and β 1 by k 1 and dividing α 2 by k 1 Can scale node V 2 by k 2 by multiplying α 2 k 1 and β 2 by k 2 and dividing α 3 by k 2 α 1 = , α 2 = , α 3 = β 1 = , β 2 = , β 3 = (36) slide 55 of 56

56 Third-Order A/D Design Example V DAC +V DAC φ 1 φ 1 φ 1 β 1 φ 2 φ 2 β 2 φ 2 β 3 + V in φ 1 φ 2 φ 2 α 1 α 1 φ 2a φ 1a φ 2a C = 1 A φ 2 φ 1 φ 2 α 2 α 2 φ 2a φ 1a φ 2a C A = 1 φ 2 φ 1 φ 2 α 3 α 3 φ 1a φ 2a φ 1a C A = 1 + V 3 C A = 1 C A = 1 C A = 1 β 1 φ 2 φ 2 β 2 φ 2 β 3 φ 1 φ 1 +V DAC + V ref V DAC φ 1 +V DAC + V 3 V DAC φ 1 slide 56 of 56

Data Converter Fundamentals

Data Converter Fundamentals David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 33 Introduction Two main types of converters Nyquist-Rate Converters Generate output