EXAMPLE DESIGN PART 1

Transcription

1 EE37 Advanced Analog ircuits Lecture 3 EXAMPLE DESIGN PART Richard Schreier richard.schreier@analog.com Trevor aldwell trevor.caldwell@utoronto.ca ourse Goals Deepen understanding of MOS analog circuit design through a top-down study of a modern analog system a delta-sigma AD Develop circuit insight through brief peeks at some nifty little circuits The circuit world is filled with many little gems that every competent designer ought to know. EE37 3-

2 Date Lecture Ref Homework 0-0- RS Introduction: MOD ST, A : MOD in Matlab RS MOD & MODN ST 3, 4, B : MOD in Matlab RS 3 Example Design: Part ST 9., JM 4 3: Sw.-level MOD T 4 S ircuits R, JM 4 4: S Integrator T 5 Amplifier Design T 6 Amplifier Design 5: S Int w/ Amp Reading Week + ISS No Lecture RS 7 Example Design: Part JM 8 Start Project RS 8 omparator & Flash AD JM T 9 Noise in S ircuits ST T 0 Matching & MM-Shaping ST , RS Advanced Σ ST 6.6, T Pipeline and SAR ADs JM 5, No Lecture Project Presentation EE Highlights (i.e. What you will learn today) MOD implementation Switched-capacitor integrator Switched- summer & DA too 3 Dynamic-range scaling 4 kt/ noise 5 Verification strategy EE37 3-4

3 desired signal f B shaped noise f B f B Review: A Σ AD System f s f s Nyquist-rate PM Data U Σ Modulator V Digital Decimator W U Loop Filter DA V(z )= STF(z )U(z )+ NTF(z )E(z ) STF(z ): signal transfer function NTF(z ): noise transfer function E(z ): quantization error EE Y E V U z Review: MOD Q E Vz ( ) = NTF( z)ez ( ) + STF( z)uz ( ) NTF( z) = ( z ) STF( z) = z NTF ( e j πf ) 4 3 ω for ω « Normalized Frequency (f /f s ) Doubling OSR improves SQNR by 9 db Peak SQNR dbp( 9 OSR 3 ( π )); dbp( x) 0log 0 ( x) EE37 3-6

4 U z z Review: MOD z Q E V NTF( z) = ( z ) STF( z) = z NTF ( e j πf ) ω 4 for ω « Normalized Frequency (f /f s ) Doubling OSR improves SQNR by 5 db Peak SQNR dbp( ( 5 OSR 5 ) ( 4π 4 )) EE dbfs/nbw Review: Simulated MOD PSD Input at 50% of FullScale 0 SQNR = 86 OSR = 8 Simulated spectrum (smoothed) 40 db/decade Theoretical PSD (k = ) NBW = Normalized Frequency (f /f s ) EE37 3-8

5 Review: Advantages of Σ AD: Simplified Anti-Alias Filter Since the input is oversampled, only very high frequencies alias to the passband. A simple R section often suffices. If a continuous-time loop filter is used, the anti-alias filter can often be eliminated altogether. DA: Simplified Reconstruction Filter The nearby images present in Nyquist-rate reconstruction can be removed digitally. + Inherent Linearity Simple structures can yield very high SNR. + Robust Implementation Σ tolerates sizable component errors. EE Let s Try Making One! lock at f s = MHz. Assume BW = khz. OSR = f s ( BW ) = MOD: SQNR 9 db/octave 9 octaves = 8 db MOD: SQNR 5 db/octave 9 octaves =35 db Actually more like 0 db. SQNR of MOD is not bad, but SQNR of MOD is awesome! In addition to MOD s SQNR advantage, MOD is usually preferred over MOD because MOD s quantization noise is more well-behaved. EE37 3-0

6 U What Do We Need? z z z Q E V Summation blocks Delaying and non-delaying discrete-time integrators 3 Quantizer (-bit) 4 Feedback DAs (-bit) 5 Decimation filter (not shown) Digital and therefore easy. EE37 3- Switched-apacitor Integrator Single-ended circuit: Vin φ φ φ φ φ Vout z Timing: φ φ φ Vin v in ( n) v in ( n + ) Vout v out ( n) v out n + Time ( ) φ EE37 3-

7 φ: q ( n) = V out ( n) q ( n) = V in ( n) Vin Vout φ: q n + q 0 ( ) = q ( n) + q ( n) Vin Vout EE q ( n + ) = q ( n) + q ( n) zq ( z) = Q ( z) + Q ( z) Q ( z) Q ( z) z This circuit integrates charge Since Q = V in and Q = V out V out ( z) V in ( z) Note that the voltage gain is controlled by a ratio of capacitors With careful layout, 0.% accuracy is possible. = = z EE37 3-4

8 V V Summation + Integration φ φ φ φ φ φ V out ( z) = φ Vout V ( z) V ( z) ( z ) z Adding an extra input branch accomplishes addition, with weighting EE b DA + Summation + Integration V +Vref Vref φ φ φ v φ v φ φ φ φ Vout z DA v EE37 3-6

9 Differential Integrator φ φ φ Vin φ φ Vout Allows V in,m (= V out,m of previous stage) to be arbitrary φ φ φ EE M of amplifier inputs Amplifier drives only capacitors, so a high output impedance is OK Non-Delaying Integrator Single-ended circuit: Swap Phases φ φ φ Vin φ φ Vout Timing: φ φ φ φ Vin v in ( n) v in ( n + ) Vout v out ( n) v out n + ( ) Integration occurs during φ EE37 3-8

10 φ: q = 0 q ( n) = V out ( n) Vin Vout φ: q ( n + ) = q ( n) q ( n + ) Vin q ( n + ) = V in ( n + ) Vout EE q ( n + ) = q ( n) q ( n + ) zq ( z) = Q ( z) zq ( z) Q ( z) Q ( z) = z z V out ( z) V in ( z) z = z Delay-free integrator (inverting) EE37 3-0

11 Half-Delay Integrator Single-ended circuit: Vin φ φ φ φ φ Sample output on φ Vout Timing: φ φ φ Vin v in ( n) v in ( n + ) Vout v out ( n) v out n + Time ( ) φ EE37 3- Half-Delay Integrator Output is sampled on a different phase than the input z Some use the notation Hz ( ) = / to denote the shift in sampling time z I consider this an abuse of notation. An alternative method is to declare that the border between time n and n+ occurs at the end of a specific phase, say φ A circuit which samples on φ and updates on φ is non-delaying, i.e. Hz ( ) = z ( z ), whereas a circuit which samples on φ and updates on φ is delaying, i.e. Hz ( ) = ( z ). EE37 3-

12 Timing in a Σ AD The safest way to deal with timing is to construct a timing diagram and verify that the circuit implements the desired difference equations E.g. MOD: un ( ) x ( n + ) x ( n + ) x ( n) z - z - x ( n) vn ( ) Q Difference Equations: v( n) = Qx ( ( n) ) x ( n + ) = x ( n) vn ( ) + un ( ) x ( n + ) = x ( n) vn ( ) + x ( n + ) (0) () () EE Switched-apacitor Realization x x Reference feedback shares input/interstage capacitor v Timing x (n) x (n+) x (n) x (n+) 0 v(n) Timing looks OK! EE37 3-4

13 Signal Swing So far, we have not paid any attention to how much swing the op amps can support, or to the magnitudes of u, V ref, x and x For simplicity, assume: the full-scale range of u is ± V, the op-amp swing is also ± V and V ref =V We still need to know the ranges of x and x in order to accomplish dynamic-range scaling EE Dynamic-Range Scaling In a linear system with known state bounds, the states can be scaled to occupy any desired range e.g. one state of original system: α β α z x β state scaled by /k: α k kβ α k z x k k β EE37 3-6

14 State Swings in MOD U Linear Theory z z X X z Q E V V = z U + ( z ) E z X = ( z U V ) = U ( z )E X = V E = z U + ( z + z )E If u is constant and e is white with power σ e = 3, then x = u, σ x = σ = 3, e x = u and σ x = 5σ = 5 3 e EE ρ x Simulated Histograms mean = 0.0 sigma = 0.67 u = ρ x mean = 0.4 sigma = u = ρ x mean = 0.70 sigma = ρ x mean =.5 sigma = EE37 3-8

15 Observations The match between simulations and our linear theory is fair for x, but poor for x x s mean and standard deviation match theory, although x s distribution does not have the triangular form that would result if e were white and uniformly-distributed in [,]. x s mean is 50-00% high, its standard deviation is ~5% low, and the distribution is weird. Our linear theory is not adequate for determining signal swings in MOD No real surprise. Linear theory does not handle overload, i.e. where x, x when u >. Is there a better theory? Yes, but it is complicated and gives minimal insight. EE MOD Simulated State Bounds 0 8 x ( 5 u ) ( u ) x 6 4 analytic bounds x u + simulation EE u

16 Scaled MOD Take x = 3 and x = 9 The first integrator should not saturate. The second integrator will not saturate for dc inputs up to 3 dbfs and possibly as high as dbfs. Our scaled version of MOD is thus U z X X /3 /3 z z 9 Q V /3 /9 Omit since sgn(ky ) = sgn(y ) EE V u First Integrator (INT) Shared Input/Reference aps +Vref Vref v v 3 V x U / 3 / 3 V z z v v +Vref Vref 3 M of V ref = M of V u How do we determine? EE37 3-3

17 kt/ Noise R v n Fact: Regardless of the value of R, the meansquare value of the voltage on is v n kt where k = J/K is Boltzmann s constant and T is the temperature in Kelvin The ms noise charge is q n = v n = kt. = EE Derivation of kt/ Noise Equipartition of Energy physical principle: In a system at thermal equilibrium, the average energy associated with any degree of freedom is kt. This applies to the kinetic energy of atoms (along each axis of motion), vibrational energy in molecules and to the potential energy in electrical components. Fact: The energy stored in a capacitor is --V So, according to equipartition, --V, or = --kt V kt = EE

18 Implications for an S Integrator Each charge/discharge operation has a random component The amplifier plays a role during phase, but we ll assume that the noise in both phases is just kt/. We ll revisit this assumption in Lecture 9. For a given cap, these random components are essentially uncorrelated, so the noise is white q q t = q +q q q = q = kt q t = q + q = kt EE Integrator Implications (cont d) This noise charge is equivalent to a noise voltage with ms value v n = kt added to the input of the integrator: v n z z This noise power is spread uniformly over all frequencies from 0 to f s The power in the band [ 0, f B ] is v n OSR EE

19 Differential Noise v n v n = v n + v n v n v n = v v n + n Twice as many switched caps twice as much noise power The input-referred noise power in our differential integrator is v n = 4kT EE INT Absolute apacitor Sizes For SNR = 00 3-dBFS input The signal power is v ( V) s = = 0.5 V 3 dbfs Therefore we want = V Since = v n OSR v n, in-band If we want 0 db more SNR, we need 0x caps EE A v n, in-band 4kT = =.33 pf v n

20 Second Integrator (INT) Separate Input and Feedback aps 3 9 X / 3 z z v v V x V ref v v 3 V x EE M of V x M of V ref M of op amp input / 9 V INT Absolute apacitor Sizes In-band noise of second integrator is greatly attenuated π = OSR INT pb edge: A ω B 3 = = apacitor sizes not dictated by thermal noise harge injection errors and desired ratio accuracy set absolute size A reasonable size for a small cap is currently ~0 ff. ω B OSR π INT noise attenuation: > OSR A 0 6 EE

21 Behavioral Schematic EE Verification Open-loop verification Loop filter omparator Since MOD is a -bit system, all that can go wrong is the polarity and the timing. Usually the timing is checked by (), so this verification step is not needed. losed-loop verification 3 Swing of internal states 4 Spectrum: SQNR, STF gain 5 Sensitivity, start-up, overload recovery, EE37 3-4

22 Loop-Filter heck Theory Open the feedback loop, set u = 0 and drive an impulse through the feedback path U =0 z z X X z Q X z z = Y z yn ( ) = { 00,,, } x ( n) = {, 3, 4, } If x is as predicted then the loop filter is correct At least for the feedback signal, which implies that the NTF will be as designed. EE V Loop Filter heck Practice * l(r) l(p) l(p) l(v) 0 X x_matlab -00 xe X x_matlab time, xe-6 Seconds *. In theory there is no difference between theory and practice. But in practice there is. EE

23 Hey! You heated! An impulse is {,0,0, }, but a binary DA can only output ±, i.e. it cannot produce a 0 Q: So how can we determine the impulse response of the loop filter through simulation? A: Do two simulations: one with v = {,,, } and one with v = {+,,, }. Then take the difference. According to superposition, the result is the response to v = {,0,0, }, so divide by. To keep the integrator states from growing too quickly, you could also use v = {,,+,, } and then v = {+,,+,, }. EE v(xp,xn) Simulated State Swings 3-dBFS ~300-Hz sine wave Swing < V p,diff - v(xp,xn).5 Swing < V p,diff time (ms) EE

24 0 db(spec) db(sqq) Unclear Spectrum freq, xe3 Hertz EE Professional Spectrum SQNR = 05 OSR = 500 dbfs/nbw Smoothed Spectrum 08-dBc 3 rd harmonic Theoretical PSD (k = ) k 0k 00k Frequency (Hz) NBW=46Hz SQNR dominated by 09-dBFS 3 rd harmonic EE

25 Implementation Summary hoose a viable S topology and manually verify timing Do dynamic-range scaling You now have a set of capacitor ratios. Verify operation: loop filter, timing, swing, spectrum. 3 Determine absolute capacitor sizes Verify noise. 4 Determine op-amp specs and construct a transistor-level schematic Verify everything. 5 Layout, fab, debug, document, get customers, sell by the millions, go public, EE Differential vs. Single-Ended Differential is more complicated and has more caps and more noise single-ended is better? ±V / ±V ± V / ( V ) SNR V V = = SNR = = 4kT ( ) 4kT kt V kT Same capacitor area same SNR Differential is generally preferred due to rejection of even-order distortion and common-mode noise/ interference. EE

26 Double-Sampled Input V u Doubles the effective input signal Allows to be 4 the size for the same SNR Doubles the sampling rate of the signal, thereby easing AAF further EE Shared vs. Separate Input aps Separate caps More noise: V input: = kt v n V V input: v n V gain / V gain: = kt v n referred to V : v n V Total noise referred to V : ( kt )( + ) But using separate caps allows input M to be different from reference M, and so is often preferred in a general-purpose AD EE37 3-5

27 Signal-Dependent Ref. Loading Another practical concern is the current draw from the reference V ref αsinωt V ref,actual V in V in V ref AD Output ( + εsinωt ) V ref ( εsinωt ) If the reference current is signal-related, harmonic distortion can result EE Shared aps and Ref. Loading +Vref Vref v v +V ref q V u V u v v +Vref Vref q = ( V ref V u ), v = + ( V ref + V u ), v = EE

28 Thus I = --- V T ( ref v Vu ) If u = Asinω u t, then v = u + error also contains a component at ω u and thus I contains a component at ω = ω u. Since AD Output V in ( + εsinωt ), the signaldependent reference current in our circuit can produce 3 rd -harmonic distortion Also, the load presented to the driving circuit is dependent on v and this noisy load can cause trouble. With separate caps, the reference current is signal-independent Yet another reason for using separate caps. EE Unipolar Reference V ref v v + v q = v V ref DA v (n ) v (n +) Be careful of the timing of v relative to the integration phase! EE

29 V u v V ref Single-Ended Input Shared aps v Full-scale range of V u is [0,V ref ]. v V ref v v (n ) v (n +) EE Homework #3 onstruct a differential switched-capacitor implementation of MOD using ideal elements (switches, capacitors, amplifiers, comparator) and verify it. Scale the circuit such that the full-scale differential input range is [,+] V and the op amp swing is 0.5 V p,diff at 6 dbfs. You may assume that 0.5-V and +0.5-V references are available and that the input is available in differential form. hoose capacitor values such that the SNR with a 6 dbfs input will be ~85 db when OSR = 8. You may assume that the only source of noise is kt/ noise. EE

30 Homework Deliverables Schematic of MOD with annotated D node voltages Open-loop impulse response plot 3 Transient of input signal and integrator outputs for a 6-dBFS input 4 Spectrum of output data for a 6-dBFS input, with SNDR calculated 5 SNDR vs. input amplitude plot 6 kt/ noise calculation (justify your choice of ) EE What You Learned Today And what the homework should solidify MOD implementation Switched-capacitor integrator Switched- summer & DA too 3 Dynamic-range scaling 4 kt/ noise 5 Verification strategy EE