Analog to Digital Conversion

Transcription

1 Analog to Digital Conversion

2 ATmega Block Diagram Analog to Digital Converter Sample and Hold SA Converter Internal Bandgap eference 2 tj

3 Analog to Digital Conversion Most of the real world is analog temperature, pressure, voltage, current, To work with these values in a computer we must convert them into digital representations Three steps to this conversion Sampling Quantizing Encoding 3 tj

4 Sampling A to D Conversion takes a finite amount of time What if the input changes during this time? We must take a snapshot of the input Sample and Hold Vin Sample Vout 4 tj

5 Sampling Sampling is a kind of MODULATION Modulation systems are subject to Aliasing Fin < fs/2 Frequency 0 Fs: Nyquist rate LPF the input (anti-aliasing filter) Frequency 0 fs Frequency 0 fs 5 tj

6 Sampling Example of analog aliasing 6 tj

7 Sampling Example of digital aliasing html 7 tj

8 Quantizing In the A to D process we are converting an infinite resolution analog signal into a finite number of digital bits Converters use reference voltages to set the range of allowed input voltages - Vref-H, Vref-L Each binary step represents (V ref-h V ref-l ) / 2 n for an n bit conversion e.g. 0V 1V input converted to 3 bit digital value each binary step represents 0.125V since 000 typically represents 0.0V, 111 represents 0.875V 8 tj

9 Quantizing Quantization error looks like noise on the signal (Quantization Noise) Dynamic ange is a measure of signal to noise ratio. (SN in db) For an AtoD the Dynamic ange is the measure of signal to Quantizing Noise ratio (SQN) SQN = 20 log 10 (2 n /(1/2 (-1/2)) = 20 log 10 2 n 8bit 48dB 10bit 60dB n steps Step Size rel to Vref-H - Vref-L SQN (db) tj

10 Encoding In AV conversion results are held in a 16bit register results can be left or right justified e.g. If result for a 10 bit conversion is left justified = DA40 right justified = 0369 esults are unsigned unsigned results indicate the measurement with respect to For the AV, = 0v 10 tj

11 A/D Conversion Example 10 bit converter with =3.0V, =0.0V If the input is 2V, what is the output code - = 3V range 10 bit converter step size = range/2 10 = mV/step 2V / mV/step = 682 steps from unsigned left Justified code = AA80 11 tj

12 Successive Approximation A to D Uses an iterative process to determine the correct digital value for the analog input equires Input (sample and held) A register to hold the current estimate of the digital value D to A converter to convert the digital estimate back to analog A comparator to determine if the estimate is above or below the actual input value Control logic to run the process Uses a binary search to find the nearest code value to the input value 12 tj

13 Successive Approximation A to D Vin + _ Clk CONTOL D to A Successive Approximation egister OUTPUT LATCH Output Code 13 tj

14 Successive Approximation A to D The control logic resets the SA before each conversion The control logic then sets the msb The DtoA converts this to ½ the reference voltage The comparator tests to see if the input is above or below this value if above, the 1 in the msb stays if below, the msb is reset to zero The control logic then sets the msb-1 bit The DtoA converts this to the appropriate voltage level The comparator tests to see if the input is above or below this value if above, the 1 stays if below, the msb-1 bit is reset to 0 The control logic then sets the msb-n bit The DtoA converts this to voltage The comparator tests to see if the input is above or below this value if above, the 1 stays if below, the msb-n bit is reset to 0 Vin Clk D to A + _ CONTOL Successive Approximation egister Output Code 14 tj OUTPUT LATCH

15 Steps relative to - A/D A to D Converter 1V, 6 bit example Test to see if input is > or < midpoint if <, clear msb if >, set msb Input DtoA output 1 xxxx SA 15 Cycle 1 tj

16 Steps relative to - A/D A to D Converter Test to see if input is > or < midpoint if <, clear msb if >, set msb Input DtoA output 0 xxxx SA 16 Cycle 1 tj

17 Steps relative to - A/D A to D Converter Test to see if input is > or < new midpoint if <, clear bit if >, set bit Input xxx SA DtoA output 17 Cycle 1 Cycle 2 tj

18 Steps relative to - A/D A to D Converter Test to see if input is > or < new midpoint if <, clear bit if >, set bit Input xxx SA DtoA output 18 Cycle 1 Cycle 2 tj

19 Steps relative to - A/D A to D Converter Test to see if input is > or < new midpoint if <, clear bit if >, set bit Input xx SA DtoA output 19 Cycle 1 Cycle 2 Cycle 3 tj

20 Steps relative to - A/D A to D Converter Test to see if input is > or < new midpoint if <, clear bit if >, set bit Input x SA DtoA output 20 Cycle 1 Cycle 2 Cycle 3 Cycle 4 tj

21 Steps relative to - A/D A to D Converter Test to see if input is > or < new midpoint if <, clear bit if >, set bit Input SA DtoA output 21 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 tj

22 D to A Converter Converts a digital word to a fixed voltage level example: 4 bit code 0000 Vout = 1111 Vout = +(-)( ) b0 contributes 1/16 b1 contributes 1/8 b2 contributes ¼ b3 contributes ½ 0110 Vout = +(-)( ) 1000 Vout = +(-)( 1 2 ) 2 b3 b2 b1 b vout 22 tj

23 D to A Converter Superposition and Thevenin Equivalents b3 vout 2 b3 b2 vout 2 2 b2 2 b1 2 b1 2 b0 2 2 b0 2 2 b0 x (-) 2 23 tj V + -

24 D to A Converter b3 2 vout b3 2 vout b2 2 b2 2 b1 2 2 b0 x (-) 2 V + - b0 x (-) 2 V + - b0 x (-) 4 24 tj V + -

25 D to A Converter b3 2 vout b3 2 vout b2 2 2 b0 x (-) 4 V + - b0 x (-) 4 V + - b0 x (-) 8 25 tj V + -

26 D to A Converter b3 2 vout 2 vout b0 x (-) 8 V + - b0 x (-) 8 V + - b0 x (-) tj V + -

27 D to A Converter b2 analysis b3 2 vout b3 2 vout b2 2 b2 2 b1 2 2 b b2 x (-) 2 27 tj V + -

28 D to A Converter b3 vout 2 2 vout b2 x (-) 2 V + - b2 x (-) 2 V + - b2 x (-) 4 28 tj V + -

29 D to A Converter Vout = ((b0)/16 + (b1)/8 + (b2)/4 + (b3)/2)(-) + 29 tj