Introduction to Phase Locked Loop (PLL) DIGITAVID, Inc. Ahmed Abu-Hajar, Ph.D.
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1 Introduction to Phase Locked Loop (PLL) DIGITAVID, Inc. Ahmed Abu-Hajar, Ph.D.
2 Presentation Outline What is Phase Locked Loop (PLL) Basic PLL System Problem of Lock Acquisition Phase/Frequency Detector (PFD) Charge Pump PLL Application of PLL
3 What is Phase Locked Loop (PLL) PLL is an Electronic Module (Circuit) that locks the phase of the output to the input. V i Phase Locked Loop V o
4 Locked Vs. Unlocked Phase Example of locked phase V i V o Example of unlocked phase V o V i Phase Error ( φ)
5 Basic PLL System PLL is a feedback system that detects the phase error φ and then adjusts the phase of the output. V i Phase Locked Loop V o V I Phase Detector φ V o The Phase Detector (PD), detects φ between the output and the input through feedback system Voltage Control Oscillator () adjusts the phase difference
6 Implementation of PD Phase Detector is an XOR gate V 1 V o φ V I Phase Detector φ V o ϕ = 1 0 V V I I V = V o o V o V i Phase Error ( φ)
7 What is? is a circuit module that oscillates at a controlled frequency ω. The Oscillating Frequency is controlled using Voltage VControl. That is why the module is called Voltage Control Oscillator ω ω 0 V Control ω ω = ω + K V V Control o Control Vcontrol must be in the steady state for the to operate properly
8 Simple PLL Structure Phase Detector ( XOR ) that detects the phase error φ Low Pass Filter ( to smooth φ ) Voltage Control Oscillator () Basic Idea If VI and Vout are out of phase (unlocked), then the PD module detects the error and the LPF smoothes the error signal. The control signal slows down or speeds up the module; hence, the phase is corrected (locked) V I Phase φ LPF V Control V out Detector φ V out
9 Locked Condition Locked Condition d dt This implies that ( ϕ ϕ ) = 0 in ω in out = ω out V I Phase φ LPF V Control V out Detector φ V out
10 Example: In the UNLOCKED State VI and Vout has φ at the same frequency ω1 The phase detector must produce VI Hence, is dynamically changing and PD is creating VControl to adjust for the phase difference. The PLL is in the Locked state V i V o Phase Error ( φ) VControl ω ω 1 ω 0 VControl V1 φ0 V 1 V Control
11 In the UNLOCKED State For Simplicity and by using Fourier Series Let ( ω ) V V cos t I = V = V cos ( ω t + ϕ ) A 1 out B 1 o Due to φ, PD creates Vcontrol will change ω = ω + K out 1 Control The output voltage becomes V out B 1 o ( ω ϕ ϕ ) V = V cos t + ( t)
12 Dynamics of Simple PLL PLL is a feedback system PD is a gain amplifier LPF be first order filter ( as an example) is a unit step module The transfer function of the feedback system is given as: Φ ω ω H ( s) = ( s) = ( s) = KPDKωLPF H ( s) = 2 Φ + + s + ω s + K K 2 out out n 2 2 in ωin s 2ςωns ωn ω LPF PD LPF φ in PD K PD LPF 1 s 1+ ω LPF K s φ out
13 Transient Response to PLL The unit step response to second order system Overdamped Critically damped ω i Underdamped Problems with this PLL Settling time Vs. ripple of Vcontor Stability of the system ω out Lacks performance in ICs 2 Φout ωout ωn H ( s) = ( s) = ( s) = Φ s + 2 s + φ in 2 2 in in LPF n n PD K PD ω ςω ω 1 s 1+ ω LPF K s φ out t t
14 Problem of Lock Acquisition When PLL is turned on, the output frequency is far from the input frequency It is possible that the PLL would never lock Modern PLL uses FREQUENCY DEDECTOR (FD) in addition to the PD. PD LPF1 V in ω in FD LPF2 V out ω out
15 Phase/Frequency Detector (PFD) One Module that detects both frequency and phase differences This module senses the transition in A or B A B QA QB A Initially A leads B XX A B QA QB Initially B leads A XX If A leads B, QA changes its state and QB remains unchanged If B leads A, QB changes its state and QA remains unchanged B PFD Q A Q B A B A B Q B Q B Q A Q A
16 Hardware Implementation of PFD Uses two Edge Triggering modules using D-FF If A leads to 1 QA = 1 When B becomes 1, QB = 1 momentarily The AND gate RESETs Both to Qs 0 A D CK Q Q A If B leads to 1 QB = 1 When A becomes 1, QA = 1 momentarily The AND gate RESETs Both to Qs 0 B D CK Q Q B
17 Hardware Implementation of PFD A B D Q Q A Q B A CK Q A RES A B Q B Q A RES B RES D CK The Vout is the average of (QA QB) is used to detect the phase and the frequency difference Q Q B
18 The Basic Block diagram Structure PFD LPF Differential Amplifier Negative Feedback Disadvantage: Sensitive to noise and offset voltages, ripple Vcontrol,.. Use Charge Pump PLL Vin φ in ω in Vout φ out ω out D CK D CK Q Q Q A Q B
19 Charge Pump PLL Structure PFD Two switches controlled by QA and QB Capacitor d V C I C = C d t Vin φ in ω in D CK Q Q A d V d t C = I C Negative Feedback It charges or discharges the capacitor indefinitely C Vout φ out ω out D CK Q Q B
20 Charge Pump PLL The capacitor is replaced with a LPF (Cp and Rp) to improve the phase margin for stability The transfer function of the system is approximated as follows: H ( s) = IPK 2π C I ( R C s + 1) 2 P P s + KRPs + K 2π 2π CP Rp slows down the system P P P I K Vin φ in ω in Vout φ out ω out D CK D CK Q Q Q A Q B C P R P
21 Application of PLL Frequency Multiplications The feedback loop has frequency division Frequency division is implemented using a counter V I PFD φ LPF V Control V out φ Clock Skew Reduction Buffers are used to distribute the clock Embed the buffer within the loop Counter (Frequency Division)
22 Application of PLL Clock Skew Reduction Buffers are used to distribute the clock Embed the buffer within the loop V I PFD φ LPF V Control V out φ V out Buffer Jitter Reduction
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